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power bank assp flash mcu HT45F5N/ht45fh5n revision: v1.00 date: ?ove??e? 1?? ?01? ?ove??e? 1?? ?01?
rev. 1.00 ? ?ove??e? 1?? ?01? rev. 1.00 3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu table of contents eates cpu featu?es ......................................................................................................................... 7 pe?iphe?al featu?es ................................................................................................................. 7 gene?al desc?iption ........................................................................................ ? selection ta?le ................................................................................................. 9 block diag?a? .................................................................................................. 9 pin assign?ent .............................................................................................. 10 pin desc?iption .............................................................................................. 1? a?solute maxi?u? ratings .......................................................................... 15 d.c. cha?acte?istics ....................................................................................... 1? a.c. cha?acte?istics ....................................................................................... 17 a/d conve?te? elect?ical cha?acte?istics ..................................................... 1? lvd / lvr elect?ical cha?acte?istics ............................................................ 19 refe?ence voltage cha?acte?istics ............................................................... 19 slew rate cont?ol cha?acte?istics ............................................................... ?0 ove? cu??ent p?otection elect?ical cha?acte?istics .................................... ?1 ove? / unde? voltage p?otection elect?ical cha?acte?istics ....................... ?1 delay lock loop elect?ical cha?acte?istics ................................................ ?? ldo regulato? elect?ical cha?acte?istics ................................................... ?? level conve?te? elect?ical cha?acte?istics .................................................. ?? usb auto detection elect?ical cha?acte?istics ........................................... ?3 lcd scom elect?ical cha?acte?istics ......................................................... ?4 powe?-on reset cha?acte?istics ................................................................... ?4 syste? a?chitectu?e ...................................................................................... ?5 clocking and pipelining ......................................................................................................... ?5 p?og?a? counte? ................................................................................................................... ?? stack ..................................................................................................................................... ?7 a?ith? etic and logic unit C alu ........................................................................................... ?7 flash p?og?a? me?o?y ................................................................................. ?? st?uctu?e ................................................................................................................................ ?? special vecto ?s ..................................................................................................................... ?? look-up ta ?le ....................................................................................................................... ?? ta ?le p?og?a? exa?ple ........................................................................................................ ?9 ta ?le read p?og?a? exa?ple .............................................................................................. ?9 in ci?cuit p?og?a??ing C icp ............................................................................................... 30 on chip de?ug suppo?t C ocds ......................................................................................... 31
rev. 1.00 ? ?ove??e? 1?? ?01? rev. 1.00 3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ram data memory ......................................................................................... 32 st?uctu?e ............................................................................................................................... 3? data me ?o?y add?essing ...................................................................................................... 33 gene?al pu?pose data me?o?y ............................................................................................ 33 special pu?pose data me?o?y ............................................................................................. 33 special function register description ........................................................ 35 indi? ect add?essing registe?s C iar0? iar1? iar? ............................................................... 35 me?o?y pointe?s C mp0? mp1l? mp1h? mp?l? mp?h ......................................................... 35 accu?ulato? C acc .............................................................................................................. 37 p?og?a? counte? low registe? C pcl ................................................................................. 37 look-up ta ? le registe? s C tblp ? tbhp ? tblh .................................................................... 37 status registe? C status ................................................................................................... 37 eeprom data memory .................................................................................. 39 eeprom data me?o?y st?uctu?e ........................................................................................ 39 eeprom registe?s .............................................................................................................. 39 reading data f?o? the eeprom ......................................................................................... 41 w ?iting data to the eeprom ................................................................................................ 41 w ?ite p?otection ..................................................................................................................... 41 eeprom inte??upt ................................................................................................................ 41 p?og?a??ing conside?ations ................................................................................................ 4? oscillators ...................................................................................................... 43 oscillato? ove?view ............................................................................................................... 43 system clock confgurations ................................................................................................ 43 inte?nal rc oscillato? C hirc ............................................................................................... 44 inte?nal 3?khz oscillato? C lirc .......................................................................................... 44 operating modes and system clocks ......................................................... 44 syste? clocks ...................................................................................................................... 44 syste? ope?ation modes ..................................................................................................... 45 cont?ol registe? .................................................................................................................... 4? ope?ating mode switching ................................................................................................... 4? stand?y cu??ent conside?ations .......................................................................................... 51 wake-up ............................................................................................................................... 5? watchdog timer ............................................................................................. 53 watchdog ti ?e? clock sou?ce .............................................................................................. 53 watchdog ti ?e? cont?ol registe? ......................................................................................... 53 watchdog ti ?e? ope?ation ................................................................................................... 54 reset and initialisation ................................................................................. 55 reset functions .................................................................................................................... 55 reset initial conditions ........................................................................................................ 57 input / output ports ...................................................................................... 62 pull-high resisto?s ................................................................................................................ ?? po? t a wake-up ..................................................................................................................... ?3 i/o po?t cont?ol registe?s ..................................................................................................... ?4 slew rate cont?ol ................................................................................................................. ?5
rev. 1.00 4 ?ove??e? 1?? ?01? rev. 1.00 5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pin-sha?ed function .............................................................................................................. ?? i/o pin st?uctu?es .................................................................................................................. 71 p?og?a??ing conside?ations ............................................................................................... 7? timer modules C tm ...................................................................................... 72 int?oduction ........................................................................................................................... 7? tm ope?ation ........................................................................................................................ 73 tm clock sou?ce ................................................................................................................... 73 tm inte??upts ......................................................................................................................... 73 tm exte?nal pins ................................................................................................................... 73 tm input/output pin selection .............................................................................................. 74 p?og?a??ing conside?ations ................................................................................................ 74 standard type tm C stm .............................................................................. 76 standa? d tm ope?ation ......................................................................................................... 7? standa? d type tm registe?s ................................................................................................. 7? standa? d type tm ope? ating modes .................................................................................... ?0 periodic type tm C ptm ............................................................................... 90 pe? iodic tm ope?ation ......................................................................................................... 90 pe? iodic type tm registe? desc?iption ................................................................................ 90 pe? iodic type tm ope? ating modes ..................................................................................... 94 analog to digital converter ....................................................................... 103 a/d conve?te? ove?view ..................................................................................................... 103 a/d conve?te? registe? desc?iption .................................................................................... 104 a/d conve?te? ope?ation .................................................................................................... 10? a/d conve?te? refe? ence voltages ..................................................................................... 109 a/d conve?te? input signals ................................................................................................ 109 conve? sion rate and ti?ing diag?a? ................................................................................ 109 su??a? y of a/d conve?sion steps ..................................................................................... 110 p?og?a??ing conside?ations ............................................................................................... 111 a/d conve?sion function ..................................................................................................... 111 a/d conve?sion p?og?a??ing exa?ples ............................................................................. 11 ? high resolution pwm generator with auto-adjust control ..................... 114 functional desc?iption .......................................................................................................... 114 high resolution pwm registe?s .......................................................................................... 115 pwm gene?ato? ................................................................................................................. 1?0 delay lock loop ................................................................................................................ 1?0 auto-adjust ci?cuit ............................................................................................................... 1?? dead-ti ?e inse?t ................................................................................................................. 1?? p?otection and inve?ting cont?ol .......................................................................................... 1?4 p?og?a??ing conside?ations .............................................................................................. 1?4 over current protection .............................................................................. 125 ove? cu??ent p?otection ope?ation ..................................................................................... 1?5 ove? cu??ent p?otection cont?ol registe?s ......................................................................... 1?? input voltage range ............................................................................................................ 130 ocpn opa and co ?pa?ato? offset cali??ation ................................................................... 130
rev. 1.00 4 ?ove??e? 1?? ?01? rev. 1.00 5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu over/under voltage protection ................................................................... 132 ouvp ci ?cuit ope?ation ...................................................................................................... 13? ouvpn registe? desc?iption ............................................................................................... 133 ovpn and uvpn co?pa?ato? offset cali??ation ................................................................ 137 usb auto detection ..................................................................................... 139 d0+/d0- fo? auto detection ................................................................................................ 140 d1+/d1- and d?+/d?- fo? auto detection ............................................................................ 140 usb auto detection registe ?s ............................................................................................ 140 serial interface module C sim ..................................................................... 144 spi inte?face ...................................................................................................................... 144 i ? c inte?face ........................................................................................................................ 150 lcd scom function ................................................................................... 160 lcd ope?ation .................................................................................................................... 1?0 lcd bias cu??ent cont?ol ................................................................................................... 1?0 interrupts ...................................................................................................... 161 inte??upt registe?s ............................................................................................................... 1?1 inte??upt ope?ation .............................................................................................................. 1?? exte?nal inte??upts ............................................................................................................... 1?? ove? cu??ent p?otection inte??upts ...................................................................................... 1?? ove? voltage p?otection inte??upts ...................................................................................... 1?? unde? voltage p?otection inte??upts .................................................................................... 1?9 multi-function inte??upts ....................................................................................................... 1?9 ti ?e? module inte??upts ...................................................................................................... 1?9 eeprom inte??upt .............................................................................................................. 170 a/d conve?te? inte??upt ....................................................................................................... 170 ti ?e base inte??upts ........................................................................................................... 170 lvd inte ??upt ....................................................................................................................... 171 se?ial inte?face module inte??upt ......................................................................................... 171 inte?? upt wake-up function ................................................................................................. 17? p?og?a??ing conside?ations .............................................................................................. 17? low voltage detector C lvd ....................................................................... 173 lvd registe ? ....................................................................................................................... 173 lvd ope ?ation ..................................................................................................................... 174 application circuits ..................................................................................... 175 instruction set .............................................................................................. 176 int?oduction ......................................................................................................................... 17? inst? uction ti?ing ................................................................................................................ 17? moving and t ?ansfe??ing data ............................................................................................. 17? a?ith?etic ope?ations .......................................................................................................... 17? logical and rotate ope?ation ............................................................................................. 177 b?anches and cont? ol t ?ansfe? ........................................................................................... 177 bit ope?ations ..................................................................................................................... 177 ta ?le read ope?ations ....................................................................................................... 177 othe? ope?ations ................................................................................................................. 177
rev. 1.00 ? ?ove??e? 1?? ?01? rev. 1.00 7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu instruction set summary ............................................................................ 178 ta ?le conventions ............................................................................................................... 17? extended inst?uction set ..................................................................................................... 1?0 instruction defnition ................................................................................... 182 ([whqghg,qvwuxfwlrqhqlwlrq ........................................................................................... 191 package information ................................................................................... 198 ?? -pin ssop (150?il) outline di?ensions ......................................................................... 199 saw type 3 ?-pin (5??5??) qf? outline di?ensions .................................................. ?00 saw type 4 ?-pin (?.5??4.5??) qf? outline di?ensions ............................................ ?01
rev. 1.00 ? ?ove??e? 1?? ?01? rev. 1.00 7 ? ove ?? e ? 1 ?? ? 01 ? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu features cpu features ? operating v oltage f sys =8mhz: 2.55v~5.5v ? up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillators internal rc C hirc internal 32khz C lirc ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one to three instruction cycles ? table read instructions ? 115 powerful instructions ? 8-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 4k16 ? ram data memory: 256 8 ? true eeprom memory: 648 ? watchdog t imer function ? 30 bidirectional i/o lines ? slew rate control for pb0~pb3 ports output ? serial interface module C spi or i 2 c ? software controlled 4-scom lines lcd driver with 1/2 bias ? three pin-shared external interrupts ? multiple t imer modules for time measure, input capture, compare match output, pwm output or single pulse output function ? high resolution pwm complementary output with dead time control ? auto-adjust pwm duty function ? two over current protection (ocp) with interrupts ? two sets of over/under voltage protection (ouvp) with interrupts ? usb auto detection function ? dual t ime-base functions for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? low voltage reset function ? low voltage detect function ? flash program memory can be re-programmed up to 100,000 times ? flash progra m memory data retention > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years ? package: 28-pin ssop, 32-pin/46-pin qfn
rev. 1.00 ? ?ove??e? 1?? ?01? rev. 1.00 9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu general description the device is a flash memory type 8-bit high performance risc architecture microcontroller. offering users the convenience of flash memory multi-programming features, this device also includes a wide range of functions and features. other memory includes an area of ram data memory as well as an area of t rue eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter, two over current protection functions, two sets of over/under voltage protection functions, high resolution pwm output with auto-adjust pwm duty function and an usb devices auto detection function . multiple and extremely fexible timer modules provide timing, pulse generation and pwm generation functions. protective features such as an internal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. the device also includes fully integrated low and high speed oscillators which are fexibly used for different applications. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. easy communication with the outside world is provided using the internal i 2 c and spi interface. while the inclusion of fexible i/o programming features, time-base functions along with many other features ensure that the device will fnd excellent use in different power bank applications. circuitry specifc to power bank applications is also fully integrated within the device. these include functions such as over and under voltage protection, over current protection and auto detect. these features combine to ensure that a minimum of external components is required to implement power bank applications, providing the benefts of reduced component count and reduced circuit board areas.
rev. 1.00 ? ?ove??e? 1?? ?01? rev. 1.00 9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu selection table most features are common to all devices and the main features distinguishing them are the i/o pin count and level shift output pins. the following table summarises the main features of each device. part no. vdd program memory data memory data eeprom i/o timer module h.r. pwm a/d auto-adjust pwm duty ht45f5? ?.55v~ 5.5v 4k1? ?5?? ?4? 30 10-?it ptm1 1?-?it stm1 1?-?it14 ? ht45fh5? ?? part no. ref. voltage ocp ouvp ldo level shift pe+ q.c 2.0 stacks package ht45f5? ? ? ? 3?qf? ??ssop ht45fh5? 5v ? ??ssop 4?qf? ? ote: h.r. pwm: high resolution and co?ple?enta? y pwm outputs with dead-ti? e cont?ol? the duty cycle ?esolution is 7.?ns when the hirc is ?mhz. block diagram 8-bit risc mcu core i 2 c spi timer modules flash program memory eeprom data memory flash/eeprom programming circuitry ram data memory time base low voltage reset watchdog timer low voltage detect interrupt controller reset circuit internal rc oscillators 12-bit a/d converter over current protection 2 over/under voltage protection 2 usb detector high resolution pwm with dead time control dll slew-rate control i/o auto-adjust pwm ldo level shift scom function for lcd for ht45fh5n only
rev. 1.00 10 ?ove??e? 1?? ?01? rev. 1.00 11 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pin assignment HT45F5N/ht45v5n 28 ssop-a ?? ?7 ?? ?5 ?4 ?3 ?? ?1 ?0 19 1? 17 1? 15 1 ? 3 4 5 ? 7 ? 9 10 11 1? 13 14 pb4/scom0 pb5/scom1 pb?/scom? pb7/scom3 pd0/a?0/d0+/sda/scs pd1/a?1/d0-/scl/sck pd?/a??/d1+ pd3/a?3/d1- pd4/a?4/d?+ pd5/a?5/d?- pa7/i?t?/a??/icpck/ocdsck pa?/i?t1/a?7/icpda/ocdsda pa1/ouvp0/a?10 pa0/ouvp1/a?11 pb3/out1l pb?/out1h pb1/out0l pb0/out0h vdd vss pc5/sda/scs/stck pc4/scl/sck pc3/ocp1 pc?/ocp1/ptp pc1/ocp0/ptp pc0/ocp0/ptck pa?/a?9/vref pa3/i?t0/a??/batv vss pb7/scom3 HT45F5N ht45v5n 32 qfn-a 1 ? 3 4 5 ? 7 ? 9 10 11 1? 13 14 15 1? 17 1? 19 ?0 ?1 ?? ?3 ?4 ?5 ?? ?7 ?? ?9 30 31 3? pb?/scom? pb5/scom1 pb4/scom0 pb3/out1l pb?/out1h pb1/out0l pb0/out0h vdd pa4/sdi/stp pa5/sdo/stp pc5/sda/scs/stck pc4/scl/sck pc3/ocp1 pc?/ocp1/ptp pc1/ocp0/ptp pc0/ocp0/ptck pa?/a?9/vref pa3/i?t0/a??/batv pa0/ouvp1/a?11 pa1/ouvp0/a?10 pa?/i?t1/a?7/ icpda/ocdsda pa7/i?t?/a??/ icpck/ocdsck pd?/sdo pd7/sdi pd0/a?0/d0+/sda/scs pd?/a??/d1+ pd1/a?1/d0 -/scl/sck pd3/a?3/d1- pd4/a?4/d?+ pd5/a?5/d?- ep vss
rev. 1.00 10 ?ove??e? 1?? ?01? rev. 1.00 11 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ht45fh5n/ht45vh5n 28 ssop-a ?? ?7 ?? ?5 ?4 ?3 ?? ?1 ?0 19 1? 17 1? 15 1 ? 3 4 5 ? 7 ? 9 10 11 1? 13 14 cx/dx ax/bx pd?/sdo pd7/sdi pd0/a?0/d0+/sda/scs pd1/a?1/d0-/scl/sck pd?/a??/d1+ pd3/a?3/d1- pd4/a?4/d?+ pd5/a?5/d?- pa7/i?t?/a??/icpck/ocdsck pa?/i?t1/a?7/icpda/ocdsda pa1/ouvp0/a?10 pa0/ouvp1/a?11 v1?/vcc1/vcc? vss v5/vdd pb0/out0h vss pa5/sdo/stp pc3/ocp1 pc?/ocp1/ptp pc1/ocp0/ptp pc0/ocp0/ptck pa?/a?9/vref pa3/i?t0/a??/batv pb1/out0l vdd cx/dx ax/bx pd?/sdo pd7/sdi pd0/a?0/d0+/sda/scs pd1/a?1/d0 -/scl/sck pd?/a??/d1+ pd3/a?3/d1- pd4/a?4/d?+ pd5/a?5/d?- pa7/i?t?/a??/icpck/ocdsck pa?/i?t1/a?7/icpda/ocdsda pa1/ouvp0/a?10 pa0/ouvp1/a?11 v1?/vcc1/vcc? s?/vss v5/vdd pb0/out0h pc4/scl/sck pc?/ocp1/ptp pc1/ocp0/ptp pc0/ocp0/ptck pa?/a?9/vref pa3/i?t0/a??/batv pb1/out0l ht45fh5n ht45vh5n 46 qfn-a 1 ? 3 4 5 ? 7 ? 9 10 11 1? 13 14 15 1? 17 1? 19 ?0 ?1 ?? 34 35 3? 37 3? 39 ?3 ?4 ?5 ?? ?7 ?? ?9 30 31 3? 33 40 41 4? 43 44 45 4? ?c ?c pc3/ocp1 pb7/scom3 pb?/scom? pb5/scom1 pb4/scom0 ?c ?c ?c ?c ?c ?c ?c ?c ?c vdd vss pa4/sdi/stp pa5/sdo/stp pc5/sda/scs/stck ep vss note: 1. if the pin-shared pin functions have multiple outputs simultaneously, the desired pin-shared function is determined by the corresponding software control bits. 2. the ocdsda and ocdsck pins are supplied for the ocds dedicated pins and as such only available for the ht45v5n/ht45vh5n device which is the ocds ev chip for theHT45F5N/ht45fh5n device. 3. the exposed pad, abbreviated as ep, is connected to ground.
rev. 1.00 1? ?ove??e? 1?? ?01? rev. 1.00 13 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pin description with the exception of the power pins and some relevant transformer control pins, all pins on the device can be referenced by their port name, e.g. pa0, pa1 etc., which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, timer module pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. note that the pin description refers to the largest package size, as a result some pins may not exist on smaller package types. pin name function opt i/t o/t descriptions pa0/ouvp1/a ? 11 pa0 pawu papu paps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. ouvp1 paps0 a? ovp/uvp 1 input a? 11 paps0 a? a/d conve?te? exte?nal signal input channel pa1/ouvp0/a ?10 pa1 pawu papu paps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. ouvp0 paps0 a? ovp/uvp 0 input a?10 paps0 a? a/d conve?te? exte?nal signal input channel pa ?/a?9/vref pa ? pawu papu paps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. a?9 paps0 a? a/d conve?te? exte?nal signal input channel vref paps0 a? adc and ovpn/ouvpn dac exte?nal ?efe?ence input pa3/i ?t0/a??/ batv pa3 pawu papu paps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. a?? paps0 a? a/d conve?te? exte?nal signal input channel batv paps0 a? batv input i?t0 paps0 i?teg i?tc0 st exte?nal inte??upt 0 input pa4/sdi/stp pa4 pawu papu paps1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. sdi paps1 prm st spi se?ial data input stp paps1 st cmos stm output pa5/sdo/stp pa5 pawu papu paps1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. sdo paps1 prm cmos spi se?ial data output stp paps1 st cmos stm output
rev. 1.00 1? ?ove??e? 1?? ?01? rev. 1.00 13 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pin name function opt i/t o/t descriptions pa ?/i?t1/a?7/ icpda/ocdsda pa ? pawu papu paps1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. a?7 paps1 a? a/d conve?te? exte?nal signal input channel i?t1 paps1 i?teg i?tc0 st exte?nal inte??upt 1 input icpda st cmos in-ci?cuit p?og?a??ing data/add?ess pin ocdsda st cmos on-chip de?ug suppo?t data/add?ess pin- fo? ev chip only. pa7/i ?t?/a??/ icpck/ocdsck pa7 pawu papu paps1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. i?t? paps1 i?teg i?tc0 st exte?nal inte??upt ? input a?? paps1 a? a/d conve?te? exte?nal signal input channel icpck st icp clock input ocdsck st ocds clock input- fo? ev chip only. pb0/out0h pb0 pbps pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. out0h pbps cmos pwm output pb1/out0l pb1 pbps pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. out0l pbps cmos pwm output pb?/out1h pb? pbps pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. out1h pbps cmos pwm output pb3/out1l pb3 pbps pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. out1l pbps cmos pwm output pb4/scom0 pb4 pbpu pbps st cmos gene?al pu?pose i/o. registe? ena?led pull-up. scom0 pbps scom scom function pin pb5/scom1 pb5 pbpu pbps st cmos gene?al pu?pose i/o. registe? ena?led pull-up. scom1 pbps scom scom function pin pb?/scom? pb? pbpu pbps st cmos gene?al pu?pose i/o. registe? ena?led pull-up. scom? pbps scom scom function pin pb7/scom3 pb7 pbpu pbps st cmos gene?al pu?pose i/o. registe? ena?led pull-up. scom3 pbps scom scom function pin pc0/ocp0/ptck pc0 pcpu pcps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ptck pcps0 st ptm input ocp0 pcps0 a? ocp0 input pc1/ocp0/ptp pc1 pcpu pcps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ptp pcps0 st cmos ptm output o? ptm captu?e input ocp0 pcps0 a? ocp0 input
rev. 1.00 14 ?ove??e? 1?? ?01? rev. 1.00 15 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pin name function opt i/t o/t descriptions pc?/ocp1/pt p pc? pcpu pcps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ptp pcps0 st cmos ptm output o? ptm captu?e input ocp1 pcps0 a? ocp1 input pc3/ocp1 pc3 pcpu pcps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ocp1 pcps0 a? ocp1 input pc4/scl/sck pc4 pcpu pcps1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. scl pcps1 prm st cmos i ? c clock line sck pcps1 prm st cmos spi se?ial clock pc5/sda/ scs / stck pc5 pcpu pcps1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. sda pcps1 st ?mos i ? c data line scs pcps1 prm st cmos spi slave select pin stck pcps1 st stm input pd0/a?0/d0+/ sda/ scs pd0 pdpu pdps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. a?0 pdps0 a? a/d conve?te? exte?nal signal input channel d0+ pdps0 a? usb d0+ 0.?v output pin sda pdps0 prm st ?mos i ? c data line scs pdps0 prm st cmos spi slave select pin pd1/a?1/d0-/ scl/sck pd1 pdpu pdps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. a?1 pdps0 a? a/d conve?te? exte?nal signal input channel d0- pdps0 a? usb powe? ?ode detection input scl pdps0 prm st ?mos i ? c clock line sck pdps0 prm st cmos spi se?ial clock pd?/a??/d1+ pd? pdpu pdps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. a?? pdps0 a? a/d conve?te? exte?nal signal input channel d1+ pdps0 a? usb dac0 output pin pd3/a?3/d1- pd3 pdpu pdps0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. a?3 pdps0 a? a/d conve?te? exte?nal signal input channel d1- pdps0 a? usb dac1 output pin pd4/a?4/d?+ pd4 pdpu pdps1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. a?4 pdps1 a? a/d conve?te? exte?nal signal input channel d?+ pdps1 a? usb dac? output pin pd5/a?5/d?- pd5 pdpu pdps1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. a?5 pdps1 a? a/d conve?te? exte?nal signal input channel d?- pdps1 a? usb dac3 output pin
rev. 1.00 14 ?ove??e? 1?? ?01? rev. 1.00 15 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pin name function opt i/t o/t descriptions pd?/sdo pd? pdpu pdps1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. sdo pdps1 prm cmos spi se?ial data output pd7/sdi pd7 pdpu pdps1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up. sdi pdps1 prm st spi se?ial data input vdd vdd pwr digital positive powe? supply. vss vss pwr digital negative powe? supply ? g?ound ht45fh5n only v5 v5 pwr 5v ldo output v1?/vcc vcc pwr ldo powe? supply and level shifte? output d?iving supply ax? bx ax? bx level shift output. inte? nally connected to pb3/out1l ?espectively cx ? dx cx ? dx level shift output. inte?nally connected to pb?/out1h ?espectively legend: i/t: input type; o/t: output type; opt: optional by register option; pwr: power; st: schmitt trigger input; cmos: cmos output; nmos: nmos output; an: analog signal; ocds: on chip debug support; icp: in circuit programming level shift input/output relationship and reset condition level shift output level shift input reset state a input = low a input = high ax? bx low high high level shift output level shift input reset state c input = low c input = high cx ? dx high low low absolute maximum ratings supply voltage ................................................................................................. v ss -0.3v to v ss +6.0v input voltage ................................................................................................... v ss - 0.3v to v dd +0.3v storage temperature .................................................................................................... -50 ? c to 125?c operating temperature .................................................................................................. -40 ? c to 85 ? c i ol total ................................................................................................................................... 120ma i oh total .................................................................................................................................. - 120ma total power dissipation ......................................................................................................... 600mw note:these are stress ratings only. stresses exceeding the range specified under "absolute maximum ratings" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability.
rev. 1.00 1? ?ove??e? 1?? ?01? rev. 1.00 17 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu d.c. characteristics ta= ?5 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope? ating voltage (hirc) f sys =f hirc =?mhz v lvr 5.5 v f sys =f hirc /?=4mhz v lvr 5.5 v f sys =f hirc /4=?mhz v lvr 5.5 v f sys =f hirc /?=1mhz v lvr 5.5 v ope? ating voltage (lirc) f sys =f lirc =3?khz v lvr 5.5 v i dd ope?ating cu??ent (hirc) 3v ?o load? all pe?iphe? als off? f sys =f hirc /?=4mhz 0.4 0.? ?a 5v 0.? 1.5 ?a 3v ?o load? all pe?iphe? als off? f sys =f hirc =?mhz 0.? 1.? ?a 5v 1.? ?.4 ?a ope?ating cu??ent (lirc) 3v ?o load? all pe?iphe? als off? f sys =f lirc =3?khz 10 ?0 a 5v 30 50 a i stb stand?y cu??ent (sleep mode) 3v ?o load? all pe?iphe? als off? wdt on 1.5 3 a 5v 3 5 a stand?y cu??ent (idle0 mode) 3v ?o load? all pe?iphe? als off? f sub on 3 5 a 5v 5 10 a stand?y cu??ent (idle1 mode? hirc) 3v ?o load? all pe?iphe? als off? f sub on? f sys =f hirc /?=4mhz 3?0 500 a 5v 700 900 a 3v ?o load? all pe?iphe? als off? f sub on? f sys =f hirc =?mhz 3?0 500 a 5v 700 1000 a v il input low voltage fo ? i/o po?ts o? input pins 5v 0 1.5 v 0 0.?v dd v v ih input high voltage fo ? i/o po?ts o? input pins 5v 3.5 5 v 0.?v dd v dd v i ol i/o po?ts sink cu??ent (except pb0 ~pb3) 3v v ol =0.1v dd ??.? 45.? ?a 5v 37.5 75 ?a i oh i/o po?ts sou?ce cu??ent (except pb0~pb3) 3v v oh =0.9v dd -5.1? -10.?4 ?a 5v -1?.? -?5.? ?a r ph pull-high resistance fo? i/o po?ts 3v ?0 ?0 100 k 5v 10 30 50 k
rev. 1.00 1? ?ove??e? 1?? ?01? rev. 1.00 17 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu a.c. characteristics ta= ?5 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys syste? clock (hirc) v lvr ~ 5.5v f sys =f hirc =?mhz ? mhz syste? clock (lirc) v lvr ~ 5.5v f sys =f lirc =3?khz 3? khz f hirc high speed inte?nal rc oscillato? (hirc) 5v ta= ?5c -?% ? +?% mhz 5v 0.5v ta=0c ~ 70c -5% ? +5% mhz 5v 0.5v ta= -40c ~ ?5c -7% ? +7% mhz v lvr ~ 5.5v ta=0c ~ 70c -7% ? +7% mhz v lvr ~ 5.5v ta= -40c ~ ?5c -10% ? +10% mhz f lirc low speed inte?nal rc oscillato? (lirc) 5v ta= ?5c -10% 3? +10% khz 5v 0.5v ta= -40c ~ ?5c -40% 3? +40% khz v lvr ~ 5.5v ta= -40c ~ ?5c -50% 3? +?0% khz t tck xtck input pin mini?u? pulse width 0.3 s t i?t exte?nal inte??upt mini?u? pulse width 10 s t rstd syste? reset delay ti?e (powe?-on reset? lvr ha ?dwa?e reset? lvr softwa ?e reset? wdt softwa ?e reset) ?.3 1?.7 33.3 ?s syste? reset delay ti?e (wdt ti ? e-out ha?dwa?e cold reset) ?.3 1?.7 33.3 ?s t sst syste? sta? t-up ti?e? pe?iod (wake-up f ?o? powe? down mode and f sys off) f sys =f hirc ~ f hirc /?4 1? t hirc f sys =f lirc ? t lirc syste? sta? t-up ti?e? pe?iod (slow mode ? normal mode) f hirc off on (hto=1) 1? t hirc syste? sta? t-up ti?e? pe?iod (wake-up f ?o? powe? down mode and f sys on) f sys =f hirc ~ f hirc /?4 ? t h f sys =f lirc ? t lirc syste? sta? t-up ti?e? pe?iod (wdt ti ? e-out ha?dwa?e cold reset) 0 t h f i?c syste? f?equency fo? i ? c standa?d mode (100khz) ?o clock de?ounce ? mhz ? syste? clocks de?ounce 4 mhz 4 syste? clocks de?ounce ? mhz syste? f?equency fo? i ? c fast mode (400khz) ?o clock de?ounce 5 mhz ? syste? clocks de?ounce 10 mhz 4 syste? clocks de?ounce ?0 mhz t sreset mini?u? softwa?e reset width to reset 45 90 1?0 s
rev. 1.00 1? ?ove??e? 1?? ?01? rev. 1.00 19 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu a/d converter electrical characteristics ope? ating te?pe?atu? e: -40 c ~?5 c ? unless othe? specify symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope? ating voltage ?.55 5.5 v v adi input voltage 0 v ref v v ref refe? ence voltage ? v dd v d?l diffe ?ential ?onlinea?ity 3v v ref =v dd ? t adck =0.5s 3 lsb 5v v ref =v dd ? t adck =0.5s 3v v ref =v dd ? t adck =10s 5v v ref =v dd ? t adck =10s i?l integ?al ?onlinea?ity 3v v ref =v dd ? t adck =0.5s 4 lsb 5v v ref =v dd ? t adck =0.5s 3v v ref =v dd ? t adck =10s 5v v ref =v dd ? t adck =10s i adc additional cu??ent fo? a/d conve?te? ena?le 3v ?o load? t adck =0.5s 1 ? ?a 5v 1.5 3 ?a t adck a/d conve?sion clock pe?iod 0.5 10 s t o??st a/d conve?te? on-to-sta? t ti?e 4 s t ads sa? pling ti?e 4 t adck t adc conve? sion ti? e (include a/d sa? ple and hold ti?e) 1? t adck gerr gain e??o? 3v v ref =v dd -4 +4 lsb 5v v ref =v dd -4 +4 lsb osrr offset e ??o? 3v v ref =v dd -4 +4 lsb 5v v ref =v dd -4 +4 lsb v r opa output voltage 5v ta= ?5c -1% ?.4 +1% v r ph pull-high resistance fo? vref 3v 0.7 1 1.5 k 5v 0.7 1 1.3 k r batv the su? of batv_r1 and batv_r ? 3v ? 4 ? k 5v ? 4 ? k rr batv the ratio of batv_r1/batv_r ? 3v -1% 1:1 +1% 5v -1% 1:1 +1% r ouvpn the su? of ouvpn_r1 and ouvpn_r0 3v 1.5 3 4.5 k 5v 1.5 3 4.5 k rr ouvpn the ratio of ouvpn_r1/ouvpn_r0 3v -?% 1:? +?% 5v -?% 1:? +?%
rev. 1.00 1? ?ove??e? 1?? ?01? rev. 1.00 19 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lvd / lvr electrical characteristics ta= ?5 c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr low voltage reset voltage lvr ena ?le -5% ?.55 +5% v v lvd low voltage detection voltage lvd ena ?le? voltage select ?.7v -5% ?.7 +5% v lvd ena ?le? voltage select 3.0v -5% 3.0 +5% lvd ena ?le? voltage select 3.3v -5% 3.3 +5% lvd ena ?le? voltage select 3.?v -5% 3.? +5% lvd ena ?le? voltage select 4.0v -5% 4.0 +5% i lvrlvdbg ope?ating cu??ent 3v lvd ena ?le? lvr ena?le? vdpo?=0 45 ?0 a 5v lvd ena ?le? lvr ena?le? vdpo?=0 ?0 90 a 3v lvd ena ?le? lvr ena?le? vdpo?=1 ?00 350 a 5v lvd ena ?le? lvr ena?le? vdpo?=1 300 450 a t lvds lvdo sta ? le ti?e for lvr enable, lvd off on 15 s t lvr mini?u? low voltage width to reset 1?0 ?40 4?0 s t lvd mini?u? low voltage width to inte??upt ?0 1?0 ?40 s i lvr additional cu??ent fo? lvr ena?le lvd disa ?le 10 a i lvd additional cu??ent fo? lvd ena?le lvd ena ?le ?0 90 a reference voltage characteristics ta= ?5 c symbol parameter test conditions min. typ. max. unit v dd conditions v bg bandgap refe? ence voltage t ?i? @v dd =3.15v -5% 1.?5 +5% v t bgs v bg tu ? n on sta? le ti?e ?o load 150 s note the v bg yodhhgh8 hhffuf
rev. 1.00 ?0 ?ove??e? 1?? ?01? rev. 1.00 ?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu slew rate control characteristics ope? ating te?pe?atu? e: -40 c ~ ?5 c ? unless othe?wise specify symbol parameter test conditions min. typ. max. unit v dd conditions i ol pb0~pb3 po?ts sink cu??ent 3v v ol = 0.?v dd ?4 ?0 ?a 5v ?0 150 ?a i oh pb0~pb3 sou?ce cu??ent 3v v oh = 0.?v dd -?4 -?0 ?a 5v -?0 -150 ?a sr rise output rising edge slew rate fo? pb0~pb3 po?ts 5v slewcn [?+1? ?] = 00b ( n = 0?1; ? = 0 o? ?) 0.5v to 4.5v ? c l oad = 1000pf ?00 v/s 5v slewcn [?+1? ?] = 0 1 b ( n = 0?1; ? = 0 o? ?) 0.5v to 4.5v ? c l oad = 1000pf 50 ?0 90 v/s 5v slewcn [?+1? ?] = 1 0b ( n = 0?1; ? = 0 o? ?) 0.5v to 4.5v ? c l oad = 1000pf ?5 30 55 v/s 5v slewcn [?+1? ?] = 11 b ( n = 0?1; ? = 0 o? ?) 0.5v to 4.5v ? c l oad = 1000pf 10 15 3? v/s sr fall output falling edge slew rate fo? pb0~pb3 po?ts 5v slewcn [?+1? ?] = 00b ( n = 0?1; ? = 0 o? ?) 4 .5v to 0 .5v ? c l oad = 1000pf ?00 v/s 5v slewcn [?+1? ?] = 0 1 b ( n = 0?1; ? = 0 o? ?) 4 .5v to 0 .5v ? c l oad = 1000pf 50 ?0 90 v/s 5v slewcn [?+1? ?] = 1 0b ( n = 0?1; ? = 0 o? ?) 4 .5v to 0 .5v ? c l oad = 1000pf ?5 30 55 v/s 5v slewcn [?+1? ?] = 11 b ( n = 0?1; ? = 0 o? ?) 4 .5v to 0 .5v ? c l oad = 1000pf 10 15 3? v/s
rev. 1.00 ?0 ?ove??e? 1?? ?01? rev. 1.00 ?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu over current protection electrical characteristics ta= ?5 c symbol parameter test conditions min. typ. max. unit v dd conditions i ocp ope?ating cu??ent 5v ocpne?[1:0]=01b? dac v ref =?.5v 730 1?50 a v os_cmp co?pa?ato? input offset voltage 5v without cali??ation (ocpncof[4:0]=10000b) -15 15 ?v 5v with cali??ation -4 4 ?v v hys hyste?esis 5v ?0 40 ?0 ?v v cm_cmp co?pa?ato? co??on mode voltage range 5v v ss v dd -1.4 v v os_opa opa input offset voltage 5v without cali??ation (ocpnoof[5:0]=100000b) -15 15 ?v 5v with cali??ation -4 4 ?v v cm_opa opa co ??on mode voltage range 3v v ss v dd -1.4 v 5v v ss v dd -1.4 v v or opa maxi ?u? output voltage range 3v v ss +0.1 v dd -0.1 v 5v v ss +0.1 v dd -0.1 v ga pga gain accu ?acy 5v all gain -5 5 % d?l diffe ?ential ?onlinea?ity 5v dac v ref =v dd 1 lsb i?l integ?al ?onlinea?ity 5v dac v ref =v dd 1.5 lsb over / under voltage protection electrical characteristics ta= ?5 c symbol parameter test conditions min. typ. max. unit v dd conditions i ouvp ope?ating cu??ent 5v uvpne?=1? ovpne?=1? dac v ref =?.5v 300 500 a v os input offset voltage 5v with cali??ation -4 4 ?v v hys hyste?esis 5v ?0 40 ?0 ?v v cm co?? on mode voltage range 5v v ss v dd - 1.4 v d?l diffe ?ential ?onlinea?ity 5v dac v ref =v dd 1 lsb i?l integ?al ?onlinea?ity 5v dac v ref =v dd 1.5 lsb
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu delay lock loop electrical characteristics ta= ?5 c symbol parameter test conditions min. typ. max. unit v dd conditions i dll ope?ating cu??ent 3v dlle?=1 0.9 1.? ?a 5v dlle?=1 1.5 ? ?a f dll ope?ating f?equency ?.?v~5.5v f hirc = ?mhz -10% ? +10% mhz t dlls dll sta ? le ti?e ?.?v~5.5v dlle? f?o? 0 to 1 ?0 30 s ldo regulator electrical characteristics c load =1f, ta = 25c symbol parameter test conditions min. typ. max. unit v dd condition v i? input voltage ? ?? v v out output voltage ta = ?5 c ? i load = 1?a? v i? = v out + 1v typ.- ?% 5 typ.+ ?% v -40 c ta < 85 c ? i load = 1?a? v i? = v out + 1v typ.- 5% 5 typ.+ 5% v v load load regulation (?ote 1) 1? a i load 30?a v i? = v out + 1v 0.09 0.1? %/?a v drop d? opout voltage (?ote ?) v out = ?%? i load = 1?a v i? = v out + ?v 100 ?v i q quiescent cu??ent ?o load? v i? = 1?v ? 4 a v li?e line regulation ?v v i? ??v ? i load = 1?a 0.? %/v tc temperature coeffcient -40 c ta < 85 c ? v i? = v out + 1v ? i load = 10?a 0.9 ? ?v/c 1rwh /rdg uhjxodwlrq lv phdvxuhg dw d frqvwdqw mxqfwlrq whpshudwxuh xvlqj sxovh whvwlqj zlwk d orz ?1 wlph dqg lv jxdudqwhhg xs wr wkh pd[lpxp srzhu glvvlsdwlrq 3rzhu glvvlsdwlrq lv ghwhuplqhg e wkh lqsxw rxwsxw gliihuhqwldo yrowdjh dqg wkh rxwsxw fxuuhqw *xdudqwhhg pd[lpxp srzhu glvvlsdwlrq zloo qrw eh dydlodeoh ryhu wkh ixoo lqsxwrxwsxw udqjh 7kh pd[lpxp doorzdeoh srzhu glvvlsdwlrq dw dq dpelhqw whpshudwxuhlv3 d d us yodh ghhg d h s yodh p h s yodh d sugfh d fdh h syodhiuphydohd 1 out level converter electrical characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd condition i source output sou?ce cu??ent of ax? bx? cx ? dx v cc =1?v ? v oh =10.4v -?0 -90 ?a i si?k output sink cu??ent of ax? bx? cx ? dx v cc =1?v ? v ol =1.?v ?0 90 ?a
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu usb auto detection electrical characteristics ta= ?5c symbol parameter test co nditions min. typ. max. unit v dd conditions v dac dac ope? ating voltage ?.? 5.5 v v dp_src d0+ output voltage d0+ output source current at 250a 0.5 0.? 0.7 v i dac dac ope?ating cu??ent 3v ?o load 0.? 0.9 ?a 5v ?o load 1.0 1.5 ?a i dacsd dac shutdown cu??ent ?o load 0.1 a ? r dac resolution ? ?its d?l dac diffe ?ential ?on linea?ity ?o load? dac ?efe?ence=v dd 1 lsb i?l dac integ?al ?on linea?ity ?o load? dac ?efe?ence=v dd ? lsb v daco output voltage range code=00h v ss v ss +0.? v code=ffh v ref -0.? v ref v v ref refe? ence voltage ? v dd v t st settling ti ?e 3v c load =50pf 5 s 5v c load =50pf 5 s r o r?r output resistance 3v 3 k 5v 5 k osrr offset e ??o? 3v v ref =v dd =3v ? data wo?d=1?? 50 ?v 5v v ref =v dd =5v ? data wo?d=1?? ?0 ?v gerr gain e??o? 3v v ref =v dd =3v ? data wo?d=1?? 50 ?v 5v v ref =v dd =5v ? data wo?d=1?? ?0 ?v i dacol output sink cu??ent 3v data wo?d=00h? v daco =0.1v ref ?0 ?a 5v data wo?d=00h? v daco =0.1v ref 40 ?a i dacoh output sou?ce cu??ent 3v data wo?d=ffh? v daco =0.9v ref ?0 ?a 5v data wo?d=ffh? v daco =0.9v ref 40 ?a i sc output sho?t-ci?cuit cu??ent 3v data wo?d=ffh 0.?5 ?a 5v data wo?d=ffh 0.40 ?a r o? analog switch on ?esistance ?etween d1+/d?+ and d1-/d?- 5v ?0 35 r pl pull-low resistance fo? d0+? d0- 5v 400 700 1400 k pull-low resistance fo? d1+? d?+? d1-? d?- 5v 15 ?0 30 k err the e??o? fo? d1+? d1-? d?+? d? - output voltage 5v dac ?efe?ence=v dd ? dac digital value=14?? d1+? d1-? d?+ o? d?- connect 150k to ground ?.57 ?.7 ?.?4 v 5v dac ?efe?ence=v dd ? dac digital value=110 ? d1+, d1-, d2+, d2- connect 150k to g?ound 1.9 ?.0 ?.1 v t vdp_srcs v dp_src tu ? n on sta? le ti?e v bg off ?00 s v bg on 5 10 s
rev. 1.00 ?4 ?ove??e? 1?? ?01? rev. 1.00 ?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lcd scom electrical characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions i bias v dd /? bias cu??ent fo? lcd 5v isel[1:0]=00b 17.5 ?5 3?.5 a 5v isel[1:0]=01b 35 50 ?5 a 5v isel[1:0]=10b 70 100 130 a 5v isel[1:0]=11b 140 ?00 ??0 a v scom v dd /? voltage fo? lcd com po?t ?.?v ~ 5.5v ?o load 0.475v dd 0.5v dd 0.5?5v dd v power-on reset characteristics ta= ?5 c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta? t voltage to ensu?e powe?-on reset 100 ?v rr por v dd rising rate to ensu?e powe?-on reset 0.035 v/?s t por mini?u? ti?e fo? v dd stays at v por to ensu?e powe?-on reset 1 ?s v dd t por rr por v por ti?e
rev. 1.00 ?4 ?ove??e? 1?? ?01? rev. 1.00 ?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the device take s advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one or two cycles for most of the standard or extended instructions respectively. the exceptions to this are branch or call instructions which need one more cycle. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either the hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. fetch inst. (pc+?) execute inst. (pc+1) oscillato? clock (syste? clock) phase clock t1 phase clock t? phase clock t3 phase clock t4 p?og?a? counte? pipelining pc pc+1 pc+? fetch inst. (pc+1) execute inst. (pc) execute inst. (pc-1) fetch inst. (pc) system clocking and pipelining
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. execute inst. 1 fetch inst. ? 1 mov a? [1?h] ? call delay 3 cpl [1?h] 4: 5: ? delay: ?op fetch inst. 1 execute inst. ? fetch inst. 3 flush pipeline fetch inst. ? execute inst. ? fetch inst. 7 instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as "jmp" or "call" that demands a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc11~pc ? pcl7~pcl0 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost. stack pointe? stack level ? stack level 1 stack level 3 : : : stack level ? p?og?a? me?o?y p?og?a? counte? botto? of stack top of stack arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa, ladd, laddm, ladc, ladcm, lsub, lsubm, lsbc, lsbcm, ldaa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla, land, landm, lor, lorm, lxor, lxorm, lcpl, lcpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc, lrr, lrra, lrrca, lrrc, lrla, lrl, lrlca, lrlc ? increment and decrement: inca, inc, deca, dec, linca, linc, ldeca, ldec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti, lsnz, lsz, lsza, lsiz, lsiz, lsdz, lsdza
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu flash program memory the program memory is the location where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, this flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of 4k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. 0000h 0004h 003ch reset inte??upt vecto? 1? ?its 0fffh program memory structure special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 0000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the corresponding table read instruction such as "tabrd [m]" or "tabrdl [m]" respectively when the memory [m] is located in sector 0. if the memory [m] is located in other sectors, the data can be retrieved from the program memory using the corresponding extended table read instruction such as "ltabrd [m]" or "ltabrdl [m]" respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. the accompanying diagram illustrates the addressing data fow of the look-up table.
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu last page o? tbhp registe? tblp registe? p?og?a? me?o?y registe? tblh use? selected registe? add?ess data 1? ?its high byte low byte table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is " 0f00h " which refers to the start address of the last page within the 4k program memory of the microcontroller. the table pointer low byte register is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address " f06h " or 6 locations after the start of the specifed page . note that the value for the table pointer is referenced to the frst address specifed by tblp and tbhp if the "tabrd [m]" or "ltabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrd [m]" or "ltabrd [m]" instruction is executed. because the tblh register i s a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,0fh ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "0f06h" transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "0f05h" transferred to ; tempreg2 and tblh in this example the data "1ah" is ; transferred to tempreg1 and data "0fh" to register tempreg2 : : org 0f00h ; sets initial address of program memory
rev. 1.00 30 ?ove??e? 1?? ?01? rev. 1.00 31 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to writer programming pin correspondence table is as follows: holtek writer pins mcu programming pins pin description icpda pa ? p?og?a??ing se?ial data/add?ess icpck pa7 p?og?a??ing clock vdd vdd powe? supply vss vss g?ound the program memory and eeprom data memory c an be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, taking control of the icpda and icpck pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. * * w?ite?_vdd icpda icpck w?ite?_vss to othe? ci?cuit vdd pa? pa7 vss w?ite? connecto? signals mcu p?og?a??ing pins note: * may be resistor or capacitor. the resistance of * must be greater than 1k? or the capacitance of * must be less than 1nf.
rev. 1.00 30 ?ove??e? 1?? ?01? rev. 1.00 31 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu on chip debug support C ocds there is an ev chip named ht45v5n which is used to emulate the HT45F5N device. the ev chip device also provides an "on-chip debug" function to debug the real mcu device during the development process. the ev chip and the real mcu device are almost functionally compatible except for "on-chip debug" function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the device will have no effect in the ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp. for more detailed ocds information, refer to the corresponding document named "holtek e-link for 8-bit mcu ocds users guide". holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip de?ug suppo?t data/add?ess input/output ocdsck ocdsck on-chip de?ug suppo?t clock input vdd vdd powe? supply vss vss g?ound
rev. 1.00 3? ?ove??e? 1?? ?01? rev. 1.00 33 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. categorized into two types, the frst of these is an area of ram where special function registers are located. these registers have fxed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. structure the overall data memory is subdivided into several sectors, all of which are implemented in 8-bit wide ram. each of the data memory sector is categorized into two types, the sp ecial purpose data memory and the general purpose data memory. the special purpose data memory registers are accessible in all sectors, with the exception of the eec register at address 40h, which is only accessible in sector 1. switching between the different data memory sectors is achieved by setting the memory pointers to the correct value. the start address of the data memory is the address 00h. special purpose data memory address general purpose data memory capacity address secto? 0: 00h~7fh secto? 1: 00h~7fh ?5? ? secto? 0: ?0h~ffh secto? 1 : ?0h~ffh special pu?pose data me?o?y gene?al pu?pose data me?o?y 00h 7fh ?0h ffh secto? 0 secto? 1 40h in secto? 1 data memory structure
rev. 1.00 3? ?ove??e? 1?? ?01? rev. 1.00 33 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu data memory addressing for this device that supports the extended instructions, there is no bank pointer for data memory addressing. for data memory the desired sector is pointed by the mp1h or mp2h register and the certain data memory address in the selected sector is specifed by the mp1l or mp2l register when using indirect addressing access. direct addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. for the accessed data memory which is located in any data memory sectors except sector 0, the extended instructions can be used to access the data memory instead of using the indirect addressing access. the main difference between standard instructions and extended instructions is that the data memory address "m" in the extended instructions can be composed of 9 bits, the high byte indicates a sector and the low byte indicates a specifc address. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user programing for both reading and writing operations. by using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value "00h".
rev. 1.00 34 ?ove??e? 1?? ?01? rev. 1.00 35 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0ah 0bh 0 ch 0 dh 0eh 0 fh 10 h 11 h 12 h 19 h 18 h 1bh 1ah 1 dh 1 ch 1 fh 1eh 13 h 14 h 15 h 16 h 17 h 20 h 21 h 22 h 29 h 28 h 2bh 2ah 2dh 2 ch 2fh 2eh 23 h 24 h 25 h 26 h 27 h 30 h 31 h 32 h 39 h 38 h 3bh 3ah 3dh 3ch 3fh 3eh 33 h 34 h 35 h 36 h 37 h 40 h 41 h 42 h 43 h 47 h 48 h 49 h 4ah 4bh 4 ch 4 dh 4eh 4 fh 50 h 51 h 52 h 58 h 53 h 54 h 55 h 56 h 57 h 60 h 61 h 44 h 45 h 46 h 59 h 5ah 5bh 5 ch 5 dh 5eh 5 fh 62 h 63 h 64 h 65 h 66 h 67 h 68 h 69 h 6ah 6bh 6 dh 6 ch 6eh 6 fh 70 h 71 h 72 h 73 h 74 h 75 h 76 h 77 h 78 h 79 h 7ah 7bh 7 dh 7 ch 7eh 7 fh : unused, read as 00 h unused iar0 mp0 iar1 mp1l acc pcl tblp tblh tbhp status pd pb pcpu pbc adj 1maxh adj 1maxl ctrl smod lvrc adj 1 bh adj 1 bl slewc1 bank 0 pbpu pdpu simc0 pac papu pawu simc1 simd sima / simc2 ouvp1pc eea eed sadoh sadc0 sadc1 adj 0 s adj 0c adj 0maxh adj 0minl adj 0bh adj 1c mp1h iar 2 mp2 l mp2 h lvdc pa simtoc sadol adj 0 dt adj 0maxl adj 0bl adj 1minh pc pcc pdc adj 0minh adj 1 dt adj 1 s adj 1 minl unused unused ptmah ptmrpl stmc1 stmdl stmdh stmrp ptmc0 ptmal stmc0 stmal ptmc1 ptmrph stmah ptmdl ptmdh bank 1 intc0 ocp1 c 0 eec pwm0p pwm0d int c 1 ouvp0c 3 intc2 intc3 mfi 0 mfi 1 ouvp0c 0 bank 0 bank 1 dll1 pwm1c ovp0 da uvp 0da ouvp0c 1 ouvp0c 2 dllc ouvp1c 3 sws 0 sws 1 ocp0 c 0 ocp0 c 1 ocp 0 da ocp0ocal ocp0ccal ocp1 c 1 ocp 1 da ocp1ocal ocp1ccal ocppc ovp1da uvp 1da ouvp1c 0 ouvp1c 1 ouvp1c 2 scomc paps 0 paps 1 pbps dll0 pwm0c pwm1p pwm1d slewc0 ouvp0pc outpc0 wdtc tbc pcps0 pcps1 pdps0 pdps1 prm aduda 0 aduda 1 aduda 2 aduda 3 aduc0 aduc1 aduc2 integ unused special purpose data memory
rev. 1.00 34 ?ove??e? 1?? ?01? rev. 1.00 35 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1, iar2 the indirect addressing registe rs, iar0, iar1 and iar2, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0, iar1 and iar2 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0, mp1l/mp1h or mp2l/mp2h. acting as a pair, iar0 and mp0 can together access data only from sector 0 while the iar1 register together with the mp1l/mp1h register pair and iar2 register together with the mp2l/mp2h register pair can access data from any data memory sector. as t he indirect addressing registers are not physically implemented, reading the indirect addressing registers will return a result of "00h" and writing to the registers will result in no operation. memory pointers C mp0, mp1l, mp1h, mp2l, mp2h five memory pointers, kno wn as mp0, mp1l, mp1h, mp2l, mp2h, are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from sector 0, while mp1l/mp1h together with iar1 and mp2l/mp2h together with iar2 are used to access data from all sectors according to the corresponding mp1h or mp2h register. direct addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example 1 data .section data adres1 db adres2 db adres3 db adres4 db block db code .section at 0 code org 00h start: mov a, 04h setup size of block mov block, a mov a, offset adres1 ; accumulator loaded with frst ram address mov mp0, a ; setup memory pointer with frst ram address clr iar0 ; clear the data at address defned by mp0
rev. 1.00 3? ?ove??e? 1?? ?01? rev. 1.00 37 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu indirect addressing program example 2 data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a, 04h ; setup size of block mov block, a mov a, 01h ; setup the memory sector mov mp1h, a mov a, offset adres1 ; accumulator loaded with frst ram address mov mp1l, a ; setup memory pointer with frst ram address loop: clr iar1 ; clear the data at address defned by mp1l inc mp1l ; increment memory pointer mp1l sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. direct addressing program example using extended instructions data .section data temp db ? code .section at 0 code org 00h start: lmov a, [m] ; move [m] data to acc lsub a, [m+1] ; compare [m] and [m+1] data snz c ; [m]>[m+1]? jmp continue ; no lmov a, [m] ; yes, exchange [m] and [m+1] data mov temp, a lmov a, [m+1] lmov [m], a mov a, temp lmov [m+1], a continue: note: here "m" is a data memory address located in any data memory sectors. for example, m=1f0h, it indicates address 0f0h in sector 1.
rev. 1.00 3? ?ove??e? 1?? ?01? rev. 1.00 37 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user - defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer s and indicate the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the sc fag, cz fag, zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/ logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the "clr wdt" or "halt" instruction. the pdf fag is affected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac, c, sc and cz fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared.
rev. 1.00 3? ?ove??e? 1?? ?01? rev. 1.00 39 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ? pdf is cleared by a system power-up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cleared by a system power-up or executing the "clr wdt" or "halt" instruction. to is set by a wdt time-out. ? cz is the operational result of different fags for different instructions. refer to register defnitions for more details. ? sc is the result of the "xor" operation which is performed by the ov fag and the msb of the current instruction operation result. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 ?a?e sc cz to pdf ov z ac c r/w r r r r r/w r/w r/w r/w por x x 0 0 x x x x "x" unknown bit 7 sc : xor operation result - performed by the ov fag and the msb of the instruction operation result. bit 6 cz : operational result of different fags for different instructions. for sub/subm/lsub/lsubm instructions, the cz fag is equal to the z fag. for sbc/sbcm/lsbc/lsbcm instructions, the cz flag is the "and" operation result which is performed by the previous operation cz fag and current operation zero fag. for other instructions, the cz fag will not be affected. bit 5 to : watchdog time-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.00 3? ?ove??e? 1?? ?01? rev. 1.00 39 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu eeprom data memory this device contains an area of internal eeprom data memory. eeprom, which stands for electrically erasable programmable read only memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 64 8 bits. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an address and a data register in sector 0 , 1 and a single control register in only sector 1. eeprom registers three registers control the overall operation of t he internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in sector 0, they can be directly accessed in the same was as any other special function register. the eec register however, being located in only sector 1, cannot be addressed directly and only can be read from or written to indirectly using the mp1l/mp1h or mp2l/mp2h memory pointer and indirect addressing register, iar1/iar2. because the eec control register is located at address 40h in sector 1, the mp1l or mp2l memory pointer must frst be set to the value 40h and the mp1h or mp2h memory pointer high byte set to the value, 01h, before any operations on the e ec register are executed. register name bit 7 6 5 4 3 2 1 0 eea d5 d4 d3 d? d1 d0 eed d7 d? d5 d4 d3 d? d1 d0 eec wre? wr rde? rd eeprom register list eea register bit 7 6 5 4 3 2 1 0 ?a?e d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 d5~d0 : data eeprom address data eeprom address bit 5 ~ bit 0
rev. 1.00 40 ?ove??e? 1?? ?01? rev. 1.00 41 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu eed register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 ?a?e wre? wr rde? rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3 wren : data eeprom write enable 0: disable 1: enable this is the data eeprom write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: write cycle has fnished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no effect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the wren, wr, rden and rd cannot be set high at the same time in one instruction. the wr and rd cannot be set high at the same time.
rev. 1.00 40 ?ove??e? 1?? ?01? rev. 1.00 41 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom to write data to the eeprom, the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register. then the write enable bit, wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the memory pointer high byte register, mp1h or mp2h, will be reset to zero, which means that data memory sector 0 will be selected. as the eeprom control register is located in sector 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section.
rev. 1.00 4? ?ove??e? 1?? ?01? rev. 1.00 43 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the write enable bit is normally cleared to zero when not writing. also the memory pointer high byte register, mp1h or mp2h, could be normally cleared to zero as this would inhibit access to sector 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly. the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the device should not enter the idle or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming examples ? reading data from the eeprom C polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer mp1l mov mp1l, a ; mp1 points to eec register mov a, 01h ; setup memory pointer mp1h mov mp1h, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr mp1h mov a, eed ; move read data to register mov read_data, a ? writing data to the eeprom C polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer mp1l mov mp1l, a ; mp1 points to eec register mov a, 01h ; setup memory pointer mp1h mov mp1h, a clr emi set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit executed immediately ; after set wren bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr mp1h
rev. 1.00 4? ?ove??e? 1?? ?01? rev. 1.00 43 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu oscillators various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, the device has the fexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. inte?nal high speed rc hirc ?mhz inte?nal low speed rc lirc 3?khz oscillator types system clock confgurations there are two methods of generating the system clock, one high speed oscillator and one low speed oscillator. the high speed oscillator is the internal 8mhz rc oscillator. the low speed oscillator is the internal 32khz rc oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the frequency of the slow speed or high speed system clock is also determined using cks2~cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. p?escale? f h high speed oscillato? low speed oscillato? f h /? f h /? f h /4 hlclk? cks?~cks0 f sys hirc lirc f sub system clock confgurations
rev. 1.00 44 ?ove??e? 1?? ?01? rev. 1.00 45 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 8mhz . device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. i t requires no external pins for its operation. internal 32khz oscillator C lirc the i nternal 32khz system oscillator is the low frequency oscillator. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency f h or low frequency f sub source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from the hirc oscillator. the low speed system clock source can be sourced from the lirc oscillator. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /8 .
rev. 1.00 44 ?ove??e? 1?? ?01? rev. 1.00 45 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu f lirc f sys /4 f tb tbck f tbc ti?e base wdt p?escale? f h high speed oscillato? low speed oscillato? f h /? f h /? f h /4 hlclk? cks?~cks0 f sys hirc lirc f sub f h device clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillation will stop to conserve the power. thus there are also no the divided frequencies of f h for peripheral circuit to use. system operation modes there are five different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep, i dle0 and idle 1 mode are used when the microcontroller cpu is switched off to conserve power. operating mode description cpu f sys f lirc f tbc ? ormal mode on f h ~f h /? on on slow mode on f sub on on idle0 mode off off on on idle1 mode off on on on sleep mode off off on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. this mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 8 , the actual ratio being selected by the cks2~cks0 and hlclk bits in the s mod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current.
rev. 1.00 4? ?ove??e? 1?? ?01? rev. 1.00 47 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from f sub . the f sub clock is derived from the lirc oscillator. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep mode the cpu will be stopped. however the flirc clock will continue to operate to keep the watchdog timer function. idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu and the system oscillator will be stopped, but the low speed oscillator will be on . idle1 mode the idle1 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the low frequency clock will be on. note: if lvden=1 and the sleep or idle mode is entered, the lvd and bandgap functions will not be disabled, and the f sub clock will be forced to open. control register the registers, smod and ctrl , are used to control the system clock and the corresponding oscillator confgurations. s mod register bit 7 6 5 4 3 2 1 0 ?a?e cks? cks1 cks0 lto hto idle? hlclk r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 1 1 bit 7~5 : system clock selection 000: f sub 001: f sub 010: undefned 011: undefned 100: undefned 101: f h / 8 110: f h / 4 111: f h / 2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source directly derived from f h or f sub , a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as "0"
rev. 1.00 4? ?ove??e? 1?? ?01? rev. 1.00 47 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 3 lto : lirc system osc sst ready fag 0: not ready 1: ready this is the low speed system oscillator sst ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will change to a high level after 1~2 cycles. bit 2 hto : hirc system osc sst ready fag 0: not ready 1: ready this is the high speed system oscillator sst ready fag which indicates when the high speed system oscillator is stable after a wake-up has occurred. the fag will change to a high level after 15~16 clock cycles if the hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /8 or f sub 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /8 or f sub clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /8 or f sub clock will be selected. when system clock switches from the f h clock to the f sub clock and the f h clock will be automatically switched off to conserve power. ?a?e fsyso? lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x" unknown bit 7 fsyson : system clock f sys control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as "0" bit 2 lvrf : lvr function reset fag described elsewhere. bit 1 lrf : lvrc control register software reset fag described elsewhere. bit 0 wrf : wdtc control register software reset fag described elsewhere.
rev. 1.00 4? ?ove??e? 1?? ?01? rev. 1.00 49 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu operating mode switching the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle0 mode, idle1 mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /8 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms. the accompanying fowchart shows what happens when the device moves between the various operating modes. normal f sys =f h ~f h /? f h on cpu ?un f sys on f tbc on f lirc on slow f sys =f sub f sub on cpu ?un f sys on f h off f tbc on f lirc on idle0 halt inst?uction executed f sys off cpu stop idle?=1 fsyso?=0 f tbc on f lirc on idle1 halt inst?uction executed cpu stop idle?=1 fsyso?=1 f sys on f tbc on f lirc on sleep halt inst?uction executed f sys off cpu stop idle?=0 f tbc off f lirc on wdt o? lvd on
rev. 1.00 4? ?ove??e? 1?? ?01? rev. 1.00 49 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by setting the hlclk bit to "0" and setting the cks2~cks0 bits to "000" or "001" in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires th is oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register. normal mode slow mode cks?~cks0 = 00xb & hlclk=0 sleep mode wdt is on? idle?=0 halt inst?uction is executed idle0 mode idle?=1? fsyso?=0 halt inst?uction is executed idle1 mode idle?=1? fsyso?=1 halt inst?uction is executed
rev. 1.00 50 ?ove??e? 1?? ?01? rev. 1.00 51 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu slow mode to normal mode switching in slow mode the system uses lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "101", "110" or "111". as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the time duration required for the high speed system oscillator stabilization is specifed in the a.c. characteristics. normal mode slow mode cks?~cks0 = 101b? 110b o? 111b as hlclk=0 o? hlclk=1 sleep mode wdt is on? idle?=0 halt inst?uction is executed idle0 mode idle?=1? fsyso?=0 halt inst?uction is executed idle1 mode idle?=1? fsyso?=1 halt inst?uction is executed entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "0"and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock will be stopped and the application program will stop at the "halt" instruction, but the wdt and lvd will remain on with the clock source coming from the f lirc clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared.
rev. 1.00 50 ?ove??e? 1?? ?01? rev. 1.00 51 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in ctrl register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction, but the time base clock and the f lirc clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in ctrl register equal to "1". when this instruction is executed under the conditions described above, the following will occur: ? the system clock, time base clock and the f lirc clock will be on and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to the device which has different package types, as there may be unbonded pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the lirc oscillator has enabled.
rev. 1.00 5? ?ove??e? 1?? ?01? rev. 1.00 53 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow when the device executes the "halt" instruction, the pdf fag will be set to 1. the pdf fag will be cleared to 0 if the device experiences a system power-up or executes the clear watchdog timer instruction. if the system is woken up by a wdt overfow, a watchdog timer reset will be initiated and the to fag will be set to 1. the to fag is set if a wdt time-out occurs and causes a wake-up that only resets the program counter and stack pointer, other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled.
rev. 1.00 5? ?ove??e? 1?? ?01? rev. 1.00 53 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock, f lirc , which is in turn supplied by the lirc oscillator. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate frequency of 32khz and this specified internal clock period can vary with v dd , temperature and process variations. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable and mcu software reset operation. wdtc register bit 7 6 5 4 3 2 1 0 ?a?e we4 we3 we? we1 we0 ws? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function software control 01010b or 10101 b : enable d other values : reset mcu when these bits are changed due to adverse environmental conditions, the microcontroller will be reset. the reset operation will be activated after t sreset time and the wrf bit in the ctrl register will be set high. bit 2~0 : wdt time-out period selection 000: 2 8 /f lirc 001: 2 10 /f lirc 010: 2 12 /f lirc 011: 2 14 /f lirc 100: 2 15 /f lirc 101: 2 16 /f lirc 110: 2 17 /f lirc 111: 2 18 /f lirc these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period. ctrl register bit 7 6 5 4 3 2 1 0 ?a?e fsyso? lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x" unknown bit 7 : system clock f sys control in idle mode described elsewhere. bit 6~3 unimplemented, read as "0" bit 2 : lvr function reset fag described elsewhere.
rev. 1.00 54 ?ove??e? 1?? ?01? rev. 1.00 55 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 1 lrf : lvrc control register software reset fag described elsewhere. bit 0 wrf : wdtc control register software reset fag 0: not occur 1: occurred this bit is set high by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to zero by the application program. watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instruction will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. there are five bits, we4~we0, in the wdtc register to enable the wdt function. when the we4~we0 bits value is equal to 01010b or 10101b, the wdt function is enabled. however, if the we4~we0 bits are changed to any other values except 01010b and 10101b, which could be caused by adverse environmental conditions such as noise, it will reset the microcontroller after t sreset time. after power on these bits will have a value of 01010b. we4 ~ we0 bits wdt function 01010b / 10101b ena?le any othe? values reset mcu watchdog timer function control under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bit fled, the second is using the watchdog timer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the watchdog timer. that is to use the single "clr wdt" instruction to clear the wdt. the maximum time out period is when the 2 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 division ratio, and a minimum timeout of 7.8ms for the 2 division ration. clr wdt instruction we4~we0 bits wdtc register reset mcu f lirc clr halt instruction lirc 8-stage divider wdt prescaler f lirc /2 8 8-to-1 mux ws2~ws0 wdt time-out watchdog timer
rev. 1.00 54 ?ove??e? 1?? ?01? rev. 1.00 55 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the watchdog timer overfows and resets. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are several ways in which a microcontroller reset can occur, through events occurring internally . power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all i/o ports will be frst set to inputs. vdd powe?-on reset sst ti?e-out t rstd note: t rstd is power-on delay, typical time=16.7ms power-on reset timing chart low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the lvr function is always enabled with a specifc lvr voltage, v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally and the lvrf bit in the ctrl register will also be set high. for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for greater than the value t lvr specifed in the lvd/lvr electrical characteristics. if the low voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value is fxed at a value of 2.55v . however the lvs7~lvs0 bits still have effects on the lvr function. if these bits are changed to any other value except some certain values defned in the lvrc register by the environmental noise, the lvr will reset the device after t sreset time. when this happens, the lrf bit in the ctrl register will be set high. after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the device enters the power down mode.
rev. 1.00 5? ?ove??e? 1?? ?01? rev. 1.00 57 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lvr inte?nal reset t rstd + t sst note: t rstd is power-on delay, typical time=16.7ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 ?a?e lvs7 lvs ? lvs5 lvs4 lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0 : lvr voltage select 01010101: 2. 55 v 00110011: 2.55v 10011001: 2.55v 10101010: 2.55v other values: mcu reset (register is reset to por value). when an actual low voltage condition occurs, an mcu reset will be generated. in this situation this register contents will remain the same after such a reset occurs. any register value, other than the defined value above, will also result in the generation of an mcu reset. the reset operation will be activated after t sreset time. however in this situation this register contents will be reset to the por value. ? c trl register bit 7 6 5 4 3 2 1 0 ?a?e fsyso? lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x" unknown bit 7 fsyson : system clock f control in idle mode described elsewhere. bit 6~3 unimplemented, read as "0" bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set high when a specifc low voltage reset situation condition occurs. this bit can only be cleared to zero by the application program. bit 1 lrf : lvrc control register software reset fag 0: not occur 1: occurred this bit is set high if the lvrc register contains any non-defned lvr voltage register values. this in effect acts like a software-reset function. this bit can only be cleared to zero by the application program. bit 0 wrf : wdtc control register software reset fag described elsewhere.
rev. 1.00 5? ?ove??e? 1?? ?01? rev. 1.00 57 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as lvr reset except that the watchdog time-out fag to will be set high. wdt ti?e-out inte?nal reset t rstd + t sst note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to zero and the to fag will be set high. refer to the a.c. characteristics for t sst details. wdt ti?e-out inte?nal reset t sst wdt time-out reset during sleep or idle mode timing chart reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 powe?-on ?eset u u lvr ?eset du?ing ?o??al o? slow mode ope?ation 1 u wdt ti ?e-out ?eset du?ing ?o??al o? slow mode ope?ation 1 1 wdt ti ?e-out ?eset du?ing idle o? sleep mode ope?ation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item conditions after reset p?og?a? counte? reset to ze?o inte??upts all inte??upts will ?e disa?led wdt clea? afte? ?eset? wdt ?egins counting ti ?e? modules ti ?e? modules will ?e tu? ned off input/output po?ts i/o po?ts will ?e setup as inputs stack pointe? stack pointe? will point to the top of the stack
rev. 1.00 5? ?ove??e? 1?? ?01? rev. 1.00 59 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register power on reset wdt time-out (normal operation) wdt time-out (halt) iar0 0000 0000 0000 0000 uuuu uuuu mp0 0000 0000 0000 0000 uuuu uuuu iar1 0000 0000 0000 0000 uuuu uuuu mp1l 0000 0000 0000 0000 uuuu uuuu mp1h 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu tbhp xxxx xxxx uuuu uuuu uuuu uuuu status xx00 xxxx xx1u uuuu uu11 uuuu iar? 0000 0000 0000 0000 uuuu uuuu mp?l 0000 0000 0000 0000 uuuu uuuu mp?h 0000 0000 0000 0000 uuuu uuuu lvdc --00 -000 --00 -000 --uu -uuu smod 000- 0011 000- 0011 uuu- uuuu ctrl 0--- -x00 0--- -000 u--- -uuu lvrc 0101 0101 0101 0101 uuuu uuuu pa 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 uuuu uuuu simc0 111- 0000 111- 0000 uuu- uuuu simc1 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx uuuu uuuu sima 0000 0000 0000 0000 uuuu uuuu simc? 0000 0000 0000 0000 uuuu uuuu simtoc 0000 0000 0000 0000 uuuu uuuu ouvp1pc 0000 0000 0000 0000 uuuu uuuu eea --00 0000 --00 0000 --uu uuuu eed 0000 0000 0000 0000 uuuu uuuu sadol(adrfs=0) xxxx ---- xxxx ---- uuuu ---- sadol(adrfs=1) xxxx xxxx xxxx xxxx uuuu uuuu sadoh(adrfs=0) xxxx xxxx xxxx xxxx uuuu uuuu sadoh (adrfs=1) ---- xxxx ---- xxxx ---- uuuu sadc0 0000 0000 0000 0000 uuuu uuuu sadc1 --00 0000 --00 0000 --uu uuuu adj0dt --00 0000 --00 0000 --uu uuuu
rev. 1.00 5? ?ove??e? 1?? ?01? rev. 1.00 59 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu register power on reset wdt time-out (normal operation) wdt time-out (halt) adj0s 0000 0000 0000 0000 uuuu uuuu adj0c 000- xx-- 000- xx-- uuu- xx-- adj0maxh ---- 0000 ---- 0000 ---- uuuu adj0maxl 0000 0000 0000 0000 uuuu uuuu adj0mi?h ---- 0000 ---- 0000 ---- uuuu adj0mi?l 0000 0000 0000 0000 uuuu uuuu adj0bh ---- 0000 ---- 0000 ---- uuuu adj0bl 0000 0000 0000 0000 uuuu uuuu adj1dt --00 0000 --00 0000 --uu uuuu adj1s 0000 0000 0000 0000 uuuu uuuu adj1c 000- xx-- 000- xx-- uuu- xx-- adj1maxh ---- 0000 ---- 0000 ---- uuuu adj1maxl 0000 0000 0000 0000 uuuu uuuu adj1mi?h ---- 0000 ---- 0000 ---- uuuu adj1mi?l 0000 0000 0000 0000 uuuu uuuu adj1bh ---- 0000 ---- 0000 ---- uuuu adj1bl 0000 0000 0000 0000 uuuu uuuu slewc1 ---- 0000 ---- 0000 ---- uuuu pb 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 uuuu uuuu pc --11 1111 --11 1111 --uu uuuu pcc --11 1111 --11 1111 --uu uuuu pcpu --00 0000 --00 0000 --uu uuuu pd 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 uuuu uuuu pdpu 0000 0000 0000 0000 uuuu uuuu pwm0p 0000 0000 0000 0000 uuuu uuuu pwm0d 0000 0000 0000 0000 uuuu uuuu dll0 0000 ---- 0000 ---- uuuu ---- pwm0c 0000 0000 0000 0000 uuuu uuuu pwm1p 0000 0000 0000 0000 uuuu uuuu pwm1d 0000 0000 0000 0000 uuuu uuuu dll1 0000 ---- 0000 ---- uuuu ---- pwm1c 0000 0000 0000 0000 uuuu uuuu ouvp0c3 0001 0000 0001 0000 uuuu uuuu ovp0da 0000 0000 0000 0000 uuuu uuuu uvp0da 0000 0000 0000 0000 uuuu uuuu ouvp0c1 --00 0000 --00 0000 --uu uuuu ouvp0c? 0001 0000 0001 0000 uuuu uuuu ouvp0c0 --00 0000 --00 0000 --uu uuuu i?teg --00 0000 --00 0000 --uu uuuu
rev. 1.00 ?0 ?ove??e? 1?? ?01? rev. 1.00 ?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu register power on reset wdt time-out (normal operation) wdt time-out (halt) i?tc0 -000 0000 -000 0000 -uuu uuuu i?tc1 0000 0000 0000 0000 uuuu uuuu i?tc? 0000 0000 0000 0000 uuuu uuuu i?tc3 0000 0000 0000 0000 uuuu uuuu mfi0 -000 -000 -000 -000 -uuu -uuu mfi1 -000 -000 -000 -000 -uuu -uuu dllc 10-- ---0 10-- ---0 uu-- ---u slewc0 ---- 0000 ---- 0000 ---- uuuu ouvp0pc 0000 0000 0000 0000 uuuu uuuu ouvp1c3 0001 0000 0001 0000 uuuu uuuu sws0 --00 0000 --00 0000 --uu uuuu sws1 ---- -000 ---- -000 ---- -uuu outpc0 0000 0000 0000 0000 uuuu uuuu wdtc 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 uuuu -uuu ocp0c0 0000 0--0 0000 0--0 uuuu u--u ocp0c1 --00 0000 --00 0000 --uu uuuu ocp0da 0000 0000 0000 0000 uuuu uuuu ocp0ocal 0010 0000 0010 0000 uuuu uuuu ocp0ccal 0001 0000 0001 0000 uuuu uuuu ocp1c0 0000 0--0 0000 0--0 uuuu u--u ocp1c1 --00 0000 --00 0000 --uu uuuu ocp1da 0000 0000 0000 0000 uuuu uuuu ocp1ocal 0010 0000 0010 0000 uuuu uuuu ocp1ccal 0001 0000 0001 0000 uuuu uuuu ocppc 0000 0000 0000 0000 uuuu uuuu ovp1da 0000 0000 0000 0000 uuuu uuuu uvp1da 0000 0000 0000 0000 uuuu uuuu ouvp1c0 --00 0000 --00 0000 --uu uuuu ouvp1c1 --00 0000 --00 0000 --uu uuuu ouvp1c? 0001 0000 0001 0000 uuuu uuuu scomc -000 ---- -000 ---- -uuu ---- paps0 0000 0000 0000 0000 uuuu uuuu paps1 0000 0000 0000 0000 uuuu uuuu pbps 0000 0000 0000 0000 uuuu uuuu pcps0 0000 0000 0000 0000 uuuu uuuu pcps1 ---- 0000 ---- 0000 ---- uuuu pdps0 0000 0000 0000 0000 uuuu uuuu pdps1 0000 0000 0000 0000 uuuu uuuu prm --00 -000 --00 -000 --uu -uuu aduda0 0000 0000 0000 0000 uuuu uuuu aduda1 0000 0000 0000 0000 uuuu uuuu
rev. 1.00 ?0 ?ove??e? 1?? ?01? rev. 1.00 ?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu register power on reset wdt time-out (normal operation) wdt time-out (halt) aduda? 0000 0000 0000 0000 uuuu uuuu aduda3 0000 0000 0000 0000 uuuu uuuu aduc0 0000 0000 0000 0000 uuuu uuuu aduc1 ---- 0000 ---- 0000 ---- uuuu aduc? --00 0000 --00 0000 --uu uuuu stmc0 0000 0--- 0000 0--- uuuu u--- stmc1 0000 0000 0000 0000 uuuu uuuu stmdl 0000 0000 0000 0000 uuuu uuuu stmdh 0000 0000 0000 0000 uuuu uuuu stmal 0000 0000 0000 0000 uuuu uuuu stmah 0000 0000 0000 0000 uuuu uuuu stmrp 0000 0000 0000 0000 uuuu uuuu ptmc0 0000 0--- 0000 0--- uuuu u--- ptmc1 0000 0000 0000 0000 uuuu uuuu ptmdl 0000 0000 0000 0000 uuuu uuuu ptmdh ---- --00 ---- --00 ---- --uu ptmal 0000 0000 0000 0000 uuuu uuuu ptmah ---- --00 ---- --00 ---- --uu ptmprl 0000 0000 0000 0000 uuuu uuuu ptmprh ---- --00 ---- --00 ---- --uu eec ---- 0000 ---- 0000 ---- uuuu note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu input / output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa~p d . these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction "mov a, [m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu ? pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 papu papu7 papu ? papu5 papu4 papu3 papu ? papu1 papu0 pa pa7 pa ? pa5 pa4 pa3 pa ? pa1 pa0 pac pac7 pac5 pac5 pac4 pac3 pac ? pac1 pac0 pbpu pbpu7 pbpu? pbpu5 pbpu4 pbpu3 pbpu? pbpu1 pbpu0 pb pb7 pb? pb5 pb4 pb3 pb? pb1 pb0 pbc pbc7 pbc? pbc5 pbc4 pbc3 pbc? pbc1 pbc0 pcpu pcpu5 pcpu4 pcpu3 pcpu? pcpu1 pcpu0 pc pc5 pc4 pc3 pc? pc1 pc0 pcc pcc5 pcc4 pcc3 pcc? pcc1 pcc0 pdpu pdpu7 pdpu? pdpu5 pdpu4 pdpu3 pdpu? pdpu1 pdpu0 pd pd7 pd? pd5 pd4 pd3 pd? pd1 pd0 pdc pdc7 pdc? pdc5 pdc4 pdc3 pdc? pdc1 pdc0 i/o basic function register list pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu~p d pu, and are implemented using weak pmos transistors. note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as a digital input or nmos output. otherwise, the pull-high resistors cannot be enabled. papu register bit 7 6 5 4 3 2 1 0 ?a?e papu7 papu ? papu5 papu4 papu3 papu ? papu1 papu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 : port a pin pull-high control 0: disable 1: enable
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pbpu register bit 7 6 5 4 3 2 1 0 ?a?e pbpu7 pbpu? pbpu5 pbpu4 pbpu3 pbpu? pbpu1 pbpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pbpu7~pbpu0 : port b pin pull-high control 0: disable 1: enable p c pu register bit 7 6 5 4 3 2 1 0 ?a?e pcpu5 pcpu4 pcpu3 pcpu? pcpu1 pcpu0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 pcpu5~pcpu0 : port c pin pull-high control 0: disable 1: enable p d pu register bit 7 6 5 4 3 2 1 0 ?a?e pdpu7 pdpu? pdpu5 pdpu4 pdpu3 pdpu? pdpu1 pdpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pdpu7~pdpu0 : port d pin pull-high control 0: disable 1: enable port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. note that the wake-up function can be controlled by the wake-up control register only when the pin- shared functional pin is selected as general purpose input/output and the mcu enters the power down mode. pawu register bit 7 6 5 4 3 2 1 0 ?a?e pawu7 pawu ? pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu7~pawu0 : port a pin wake-up control 0: disable 1: enable
rev. 1.00 ?4 ?ove??e? 1?? ?01? rev. 1.00 ?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu i/o port control registers each i/o port has its own control register known as pac~p d c, to control the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 ?a?e pac7 pac ? pac5 pac4 pac3 pac ? pac1 pac0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 : port a pin input/output type selection 0: output 1: input pbc register bit 7 6 5 4 3 2 1 0 ?a?e pbc7 pbc? pbc5 pbc4 pbc3 pbc? pbc1 pbc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 : port b pin input/output type selection 0: output 1: input p c c register bit 7 6 5 4 3 2 1 0 ?a?e pcc5 pcc4 pcc3 pcc? pcc1 pcc0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as "0" bit 5~0 : port c pin input/output type selection 0: output 1: input p d c register bit 7 6 5 4 3 2 1 0 ?a?e pdc7 pdc? pdc5 pdc4 pdc3 pdc? pdc1 pdc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 : port d pin input/output type selection 0: output 1: input
rev. 1.00 ?4 ?ove??e? 1?? ?01? rev. 1.00 ?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu slew rate control the pb0~pb3 ports can be setup to have a choice of various slew rate using the slewc0 and slewc1 registers. refer to the slew rate control characteristics section to obtain the exact value for different applications. register name bit 7 6 5 4 3 2 1 0 slewc0 slewc03 slewc0? slewc01 slewc00 slewc1 slewc13 slewc1? slewc11 slewc10 slew rate control register list slewc0 register bit 7 6 5 4 3 2 1 0 ?a?e slewc03 slewc0? slewc01 slewc00 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 3~2 slewc03~slewc02 : pb2 output slew rate selection 00: slew rate=level 0 01: slew rate=level 1 10: slew rate=level 2 11: slew rate=level 3 bit 1~0 slewc01~slewc00 : pb0 output slew rate selection 00: slew rate=level 0 01: slew rate=level 1 10: slew rate=level 2 11: slew rate=level 3 note: users should refer to the slew rate control characteristics section to obtain the exact value for different applications. slewc1 register bit 7 6 5 4 3 2 1 0 ?a?e slewc13 slewc1? slewc11 slewc10 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 3~2 slewc13~slewc12 : pb3 output slew rate selection 00: slew rate=level 0 01: slew rate=level 1 10: slew rate=level 2 11: slew rate=level 3 bit 1~0 slewc11~slewc10 : pb1 output slew rate selection 00: slew rate=level 0 01: slew rate=level 1 10: slew rate=level 2 11: slew rate=level 3 note: users should refer to the slew rate control characteristics section to obtain the exact value for different applications.
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pin-shared function the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. for these pins, the desired function of the multi-function i/o pins is selected by a series of registers via the application program control. pin-shared function selection registers the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pin to share several different functions and providing a means of function selection , a wide range of different functions can be incorporated into even relatively small package sizes. the device includes port "x" output function selection register "n", labeled as px p sn, and some pin function selection register, prm, which can select the desired functions of the multi-function pin-shared pins the most important point to note is to make sure that the desired pin-shared function is properly selected and also deselected. to select the desired pin-shared function, the pin-shared function should frst be correctly selected using the corresponding pin-shared control register. after that the corresponding peripheral functional setting should be confgured and then the peripheral function can be enabled. to correctly deselect the pin-shared function, the peripheral function should frst be disabled and then the corresponding pin-shared function control register can be modifed to select other pin-shared functions. register name bit 7 6 5 4 3 2 1 0 paps0 pas31 pas30 pas ?1 pas ?0 pas11 pas10 pas01 pas00 paps1 pas7 1 pas7 0 pas ?1 pas ? 0 pas5 1 pas50 pas41 pas40 pbps pbs7 pbs? pbs5 pbs4 pbs3 pbs? pbs1 pbs0 pcps0 pcs31 pcs30 pcs?1 pcs?0 pcs11 pcs10 pcs01 pcs00 pcps1 pcs51 pcs50 pcs41 pcs40 pdps0 pds31 pds30 pds?1 pds?0 pds11 pds10 pds01 pds00 pdps1 pds71 pds70 pds?1 pds?0 pds51 pds50 pds41 pds40 prm sdiprm sdoprm scsbprm scksclprm sdaprm pin-shared function selection register list paps0 register bit 7 6 5 4 3 2 1 0 ?a?e pas31 pas30 pas ?1 pas ?0 pas11 pas10 pas01 pas00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : pa3 pin-shared function selection 00: pa3 /int0 01: an8/batv 10: pa3 /int0 11: pa3 /int0 bit 5~4 : pa2 pin-shared function selection 00: pa2 01: an9 10: vref 11: pa 2
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 3~2 pas1[1:0] : pa1 pin-shared function selection 00: pa1 01: ouvp0/an10 10: pa1 11: pa1 bit 1~0 pas0[1:0] : pa0 pin-shared function selection 00: pa0 01: ouvp1/an11 10: pa0 11: pa 0 paps1 register bit 7 6 5 4 3 2 1 0 ?a?e pas7 1 pas7 0 pas ?1 pas ? 0 pas5 1 pas50 pas41 pas40 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pas7[1:0] : pa7 pin-shared function selection 00: pa 7/int2 01: an6 10: pa 7/int2 11: pa 7/int2 bit 5~4 pas6[1:0] : pa6 pin-shared function selection 00: pa 6/int1 01: an7 10: pa 6/int1 11: pa 6/int1 bit 3~2 pas5[1:0] : pa5 pin-shared function selection 00: pa 5 01: 10: 11: undefned bit 1~0 pas4[1:0] : pa4 pin-shared function selection 00: pa 4 01: 10: 11: undefned pbps register bit 7 6 5 4 3 2 1 0 ?a?e pbs7 pbs? pbs5 pbs4 pbs3 pbs? pbs1 pbs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pbs7 : pb7 pin-shared function selection 0: pb 7 1: scom3 bit 6 pbs6 : pb6 pin-shared function selection 0: pb 6 1: scom2 bit 5 pbs5 : pb5 pin-shared function selection 0: pb 5 1: scom1
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 4 pbs4 : pb4 pin-shared function selection 0: pb 4 1: scom0 bit 3 pbs3 : pb3 pin-shared function selection 0: pb 3 1: out1l bit 2 pbs2 : pb2 pin-shared function selection 0: pb 2 1: out1h bit 1 pbs1 : pb1 pin-shared function selection 0: pb 1 1: out0l bit 0 pbs0 : pb0 pin-shared function selection 0: pb 0 1: out0h ?a?e pcs31 pcs30 pcs?1 pcs?0 pcs11 pcs10 pcs01 pcs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pcs3[1:0] : pc3 pin-shared function selection 00: p c 3 01: ocp1 10: p c 3 11: p c 3 note: if pcs3[1:0]=01 & pcs2[1:0]=01, both the pins can be used for ocp1 input at the same time. bit 5~4 pcs2[1:0] : pc2 pin-shared function selection 00: p c 2 01: ocp1 10: ptp 11: pc 2 note: if pcs3[1:0]=01 & pcs2[1:0]=01, both the pins can be used for ocp1 input at the same time. bit 3~2 pcs1[1:0] : pc1 pin-shared function selection 00: p c 1 01: ocp0 10: ptp 11: pc1 note: if pcs1[1:0]=01 & pcs0[1:0]=01, both the pins can be used for ocp0 input at the same time. bit 1~0 pcs0[1:0] : pc0 pin-shared function selection 00: p c 0 /ptck 01: ocp0 10: pc0/ptck 11: pc0/ptck note: if pcs1[1:0]=01 & pcs0[1:0]=01, both the pins can be used for ocp0 input at the same time.
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pcps1 register bit 7 6 5 4 3 2 1 0 ?a?e pcs51 pcs50 pcs41 pcs40 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3~2 pcs5[1:0] : pc5 pin-shared function selection 00: p c5/stck 01: sda 10: scs 11: p c5/stck bit 1~0 pcs4[1:0] : pc4 pin-shared function selection 00: p c4 01: scl/sck 10: p c4 11: p c4 pdps0 register bit 7 6 5 4 3 2 1 0 ?a?e pds31 pds30 pds?1 pds?0 pds11 pds10 pds01 pds00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pds3[1:0] : pd3 pin-shared function selection 00: p 3 01: an3 10: d1- 11: p 3 bit 5~4 pds2[1:0] : pd2 pin-shared function selection 00: p 2 01: an2 10: 11: 2 bit 3~2 pds1[1:0] : pd1 pin-shared function selection 00: p 01: an1/d0- 10: scl/sck 11: bit 1~0 pds0[1:0] : pd0 pin-shared function selection 00: p 0 01: an0/d0+ (usb d0+ 0.6v output pin) 10: sda 11: scs
rev. 1.00 70 ?ove??e? 1?? ?01? rev. 1.00 71 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pdps1 register bit 7 6 5 4 3 2 1 0 ?a?e pds71 pds70 pds?1 pds?0 pds51 pds50 pds41 pds40 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pds7[1:0] : pd7 pin-shared function selection 00: p d7 01: sdi 10: p d7 11: p d7 bit 5~4 pds6[1:0] : pd6 pin-shared function selection 00: p d6 01: 10: p d6 11: p d6 bit 3~2 pds5[1:0] : pd5 pin-shared function selection 00: p d5 01: an5 10: d2- 11: p d5 bit 1~0 pds4[1:0] : pd4 pin-shared function selection 00: p d4 01: an4 10: d2+ 11: p d4 prm register bit 7 6 5 4 3 2 1 0 ?a?e sdiprm sdoprm scsbprm scksclprm sdaprm r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 sdiprm : sdi pin remap control 0: sdi on pa4 1: sdi on pd7 bit 4 sdoprm : sdo pin remap control 0: sdo on pa5 1: do on pd6 bit 3 unimplemented, read as "0" bit 2 scsbprm : scs pin remap control 0: scs on pc5 1: scs on pd0 bit 1 scksclprm : sck/scl pin remap control 0: sck/scl on pc4 1: sck/scl on pd1 bit 0 sdaprm : sda pin remap control 0: sda on pc5 1: sda on pd0
rev. 1.00 70 ?ove??e? 1?? ?01? rev. 1.00 71 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. m u x vdd cont?ol bit data bit data bus w?ite cont?ol registe? chip reset read cont?ol registe? read data registe? w?ite data registe? syste? wake-up wake-up select pa only i/o pin weak pull-up pull-high registe? select q d ck q d ck q q s s generic input/output structure analog input selecto? m u x vdd cont?ol bit data bit data bus w?ite cont?ol registe? chip reset read cont?ol registe? read data registe? w?ite data registe? to a/d conve?te? a/d input po?t weak pull-up pull-high registe? select q d ck q d ck q q s s acs3~acs0 a/d input/output structure
rev. 1.00 7? ?ove??e? 1?? ?01? rev. 1.00 73 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, pac~p d c, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa~p d , are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions the device includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has two individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual standard and periodic tm section. introduction the device contains a 16-bit standard tm and a 10-bit periodic tm, having a reference name of stm and ptm. although similar in nature, the different tm types vary in their feature complexity. the common features to the standard and periodic tms will be described in this section and the detailed operation will be described in corresponding sections. the main features and differences between the two types of tms are summarised in the accompanying table. function stm ptm ti ?e?/counte? i/p captu ?e co?pa?e match output pwm channels 1 1 single pulse output 1 1 pwm align ?ent edge edge pwm adjust ?ent pe?iod & duty duty o? pe?iod duty o? pe?iod tm function summary
rev. 1.00 7? ?ove??e? 1?? ?01? rev. 1.00 73 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu tm operation the two different types of tms offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the xtck2~ xtck0 bits in the xtm control registers, where "x" stands for s or p type tm. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external xtck pin. the xtck pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the two different types of tms have two internal interrupts, the internal comparator a or comparator p, which generates a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label xtck. the tm input pin, is essentially a clock source for the tm and is selected using the xtck2~ xtck0 bits in the xtmc0 register. this external tm input pin allows an external clock source to drive the internal tm. the tm input pin can be chosen to have either a rising or falling active edge. the stck and ptck pins are also used as the external trigger input pin in single pulse output mode. another pin xtp, which also can be the xtm output pin, is the capture input pin whose active edge can be a rising edge, a falling edge or both rising and falling edges. the active edge transition type is selected using the xtio1~xtio0 bits in the xtmc1 register. for the ptm, there is another capture input, ptck, for ptm capture input mode, which can be used as the external trigger input source except for the ptp pin. the tms each have two output pins, named xtp. the tm output pins can be selected using the corresponding pin-shared function selection bits described in the pin-shared function section. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external xtp output pin is also the pin where the tm generates the pwm output waveform. as the tm input or output pins are pin-shared with other functions, the tm external pin function must first be setup using registers. a single bit in the pin-shared function selection registers determines if its associated pin is to be used as an external tm pin or if it is to have another function. stm ptm input output input output stck o? stp stp ptck o? ptp ptp tm external pins
rev. 1.00 74 ?ove??e? 1?? ?01? rev. 1.00 75 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu tm input/output pin selection selecting to have a tm input/output or whether to retain its other shared function is implemented using the relevant pin-shared function selection registers, with the corresponding selection bits in each pin-shared function register corresponding to a tm input/output pin. confguring the selection bits correctly will setup the corresponding pin as a tm input/output. the details of the pin-shared function selection are described in the p in-shared f unction section. stm stck stp ccr captu?e input ccr output tck input s tm function pin control block diagram ptm ptck ptp ccr captu?e input ccr output ccr captu?e input tck input ptm function pin control block diagram programming considerations the tm counter registers and the capture/compare ccra and ccrp registers, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing the register is carried out in a specifc way described above, it is recommended to use the "mov" instruction to access the ccra and ccrp low byte registers, named x tmal and ptmrpl, using the following access procedures. accessing the ccra or ccrp low byte register without following these access procedures will result in unpredictable values.
rev. 1.00 74 ?ove??e? 1?? ?01? rev. 1.00 75 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu data bus ?-?it buffe? xtmdh xtmdl xtmah xtmal xtm counte? registe? (read only) xtm ccra registe? (read/w?ite) ptmrph ptmrpl ptm ccrp registe? (read/w?ite) the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. write data to low byte xtmal or ptmrpl C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte xtmah or ptmrph C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte xtmdh, xtmah or ptmrph C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte xtmdl, xtmal or ptmrpl C this step reads data from the 8-bit buffer.
rev. 1.00 7? ?ove??e? 1?? ?01? rev. 1.00 77 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu standard type tm C stm the standard type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. f sys f sys /4 f h /?4 f h /1? 000 001 010 011 100 101 110 111 stck?~stck0 1?-?it count-up counte? ?-?it co?pa?ato? p ccrp ??~?15 ?0~?15 1?-?it co?pa?ato? a sto? stpau co?pa?ato? a match co?pa?ato? p match counte? clea? 0 1 output cont?ol pola?ity cont?ol stp pin input/output stp stoc stm1? stm0 stio1? stio0 stmaf inte??upt stmpf inte??upt stpol ccra stcclr edge detecto? stio1? stio0 f tbc stck f tbc standard type tm block diagram standard tm operation the size of standard tm is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is 8-bit wide whose value is compared with the highest 8 bits in the counter while the ccra is the 16 bits and therefore compares with all counter bits. the only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the ston bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a stm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources and can also control an output pin. all operating setup conditions are selected using relevant internal registers. standard type tm registers overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit ccra value. one register stmrp is used to store the 8-bit ccrp value. the remaining two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 stmc0 stpau stck? stck1 stck0 sto ? stmc1 stm1 stm0 stio1 stio0 stoc stpol stdpx stcclr stmdl d7 d? d5 d4 d3 d? d1 d0 stmdh d15 d14 d13 d1? d11 d10 d9 d? stmal d7 d? d5 d4 d3 d? d1 d0 stmah d15 d14 d13 d1? d11 d10 d9 d? stmrp d7 d? d5 d4 d3 d? d1 d0 16-bit standard tm register list
rev. 1.00 7? ?ove??e? 1?? ?01? rev. 1.00 77 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu stmc0 register bit 7 6 5 4 3 2 1 0 ?a?e stpau stck? stck1 stck0 sto ? r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 stpau : stm counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the stm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 stck2~stck0 : select stm counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f tbc 101: f tbc 110: stck rising edge clock 111: stck falling edge clock these three bits are used to select the clock source for the stm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, while f and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 ston : stm counter on/off control 0: off 1: on this bit controls the overall on/off function of the stm. setting the bit high enables the counter to run, clearing the bit disables the stm. clearing this bit to zero will stop the counter from counting and turn off the stm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the stm is in the compare match output mode or the pwm output mode or single pulse output mode then the stm output pin will be reset to its initial condition, as specifed by the stoc bit, when the ston bit changes from low to high. bit 2~0 unimplemented, read as "0" stmc1 register bit 7 6 5 4 3 2 1 0 ?a?e stm1 stm0 stio1 stio0 stoc stpol stdpx stcclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 stm1~ stm0 : select stm operating mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the stm. to ensure reliable operation the stm should be switched off before any changes are made to the stm1 and stm0 bits. in the timer/counter mode, the stm output pin state is undefned.
rev. 1.00 7? ?ove??e? 1?? ?01? rev. 1.00 79 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 5~4 stio1~ stio0 : select stm external pin function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm output mode/ single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of stp 01: input capture at falling edge of stp 10: input capture at falling/rising edge of stp 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the stm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the stm is running. in the compare match output mode, the stio1~stio0 bits determine how the stm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the stio1~stio0 bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the stoc bit. note that the output level requested by the stio1~stio0 bits must be different from the initial value setup using the stoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the ston bit from low to high. in the pwm mode, the stio1 and stio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the stio1 and stio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the stio1 and stio0 bits are changed when the tm is running. bit 3 stoc : stm output pin control bit compare match output mode 0: initial low 1: initial high pwm output mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the stm output pin. its operation depends upon whether stm is being used in the compare match output mode or in the pwm output mode/ single pulse output mode. it has no effect if the stm is in the timer/ counter mode. in the compare match output mode it determines the logic level of the stm output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low. in the single pulse output mode it determines the logic level of the stm output pin when the ston bit changes from low to high. bit 2 stpol : stm output polarity control 0: non-invert 1: invert this bit controls the polarity of the stm output pin. when the bit is set high the stm output pin will be inverted and not inverted when the bit is zero. it has no effect if the stm is in the timer/counter mode.
rev. 1.00 7? ?ove??e? 1?? ?01? rev. 1.00 79 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 1 stdpx : stm pwm period/duty control 0: ccrp C period; ccra - duty 1: ccrp C duty; ccra - period this bit determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 stcclr : select stm counter clear condition selection 0: comparator p match 1: comparator a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the stcclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the stcclr bit is not used in the pwm output mode, single pulse or input capture mode. stm dl register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 stm counter low byte register bit 7 ~ bit 0 stm 16-bit counter bit 7 ~ bit 0 stmdh register bit 7 6 5 4 3 2 1 0 ?a?e d15 d14 d13 d1? d11 d10 d9 d? r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 stm counter high byte register bit 7 ~ bit 0 stm 16-bit counter bit 15 ~ bit 8 stmal register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stm ccra low byte register bit 7 ~ bit 0 stm 16-bit ccra bit 7 ~ bit 0 stmah register bit 7 6 5 4 3 2 1 0 ?a?e d15 d14 d13 d1? d11 d10 d9 d? r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stm ccra high byte register bit 7 ~ bit 0 stm 16-bit ccra bit 15 ~ bit 8
rev. 1.00 ?0 ?ove??e? 1?? ?01? rev. 1.00 ?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu stmrp register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 d7~d0 : stm ccrp 8-bit register, compared with the stm counter bit 15 ~ bit 8. comparator p match period = 0: 65536 stm clocks 1~255: 256 (1~255) stm clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counter?s highest eight bits. the result of this comparison can be selected to clear the internal counter if the stcclr bit is cleared to zero. clearing the stcclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. standard type tm operating modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the stm1 and stm0 bits in the stmc1 register. compare output mode to select this mode, bits stm1 and stm0 in the stmc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the stcclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both stmaf and stmpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the stcclr bit in the stmc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the stmaf interrupt request fag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when stcclr is high no stmpf interrupt request fag will be generated. in the compare match output mode, the ccra cannot be set to "0". as the name of the mode suggests, after a comparison is made, the stm output pin, will change state. the stm output pin condition however only changes state when an stmaf interrupt request fag is generated after a compare match occurs from comparator a. the stmpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the stm output pin. the way in which the stm output pin changes state are determined by the condition of the stio1 and stio0 bits in the stmc1 register. the stm output pin can be selected using the stio1 and stio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the stm output pin, which is setup after the ston bit changes from low to high, is setup using the stoc bit. note that if the stio1 and stio0 bits are zero then no pin change will take place.
rev. 1.00 ?0 ?ove??e? 1?? ?01? rev. 1.00 ?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counte? value 0xffff ccrp ccra sto? stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? clea?ed ?y ccrp value pause resu?e stop counte? resta?t stcclr = 0; stm [1:0] = 00 output pin set to initial level low if stoc=0 output toggle with stmaf flag ?ote stio [1:0] = 10 active high output select he?e stio [1:0] = 11 toggle output select output not affected ?y stmaf flag. re?ains high until ?eset ?y sto? ?it output pin reset to initial value output cont?olled ?y othe? pin-sha?ed function output inve?ts when stpol is high compare match output mode C stcclr=0 note: 1. with stcclr=0 a comparator p match will clear the counter 2. the tm output pin controlled only by the stmaf fag 3. the output pin reset to initial state by a ston bit rising edge
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counte? value 0xffff ccrp ccra sto? stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? clea?ed ?y ccra value pause resu?e stop counte? resta?t stcclr = 1; stm [1:0] = 00 output pin set to initial level low if stoc=0 output toggle with stmaf flag ?ote stio [1:0] = 10 active high output select he?e stio [1:0] = 11 toggle output select output not affected ?y stmaf flag. re?ains high until ?eset ?y sto? ?it output pin reset to initial value output cont?olled ?y othe? pin-sha?ed function output inve?ts when stpol is high stmpf not gene?ated ?o stmaf flag gene?ated on ccra ove?flow output does not change compare match output mode C stcclr=1 note: 1. with stcclr=1 a comparator a match will clear the counter 2. the stm output pin controlled only by the stmaf fag 3. the output pin reset to initial state by a ston rising edge 4. the stmpf fag is not generated when stcclr=1
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu timer/counter mode to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the stm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the stm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function by setting pin-share function register. pwm output mode to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 10 respectively and also the stio1 and stio0 bits should be set to 10 respectively. the pwm function within the stm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the stm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm output mode, the stcclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the stdpx bit in the stmc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the stoc bit in the stmc1 register is used to select the required polarity of the pwm waveform while the two stio1 and stio0 bits are used to enable the pwm output or to force the stm output pin to a fxed high or low level. the stpol bit is used to reverse the polarity of the pwm output waveform. ? 16-bit stm, pwm mode, edge-aligned mode, stdpx=0 ccrp 1~255 0 pe?iod ccrp ?5? ?553? duty ccra if f sys =8mhz, stm clock source is f sys /4, ccrp=2 and ccra =128, the stm pwm output frequency=(f sys /4)/(2 256)=f sys /2048=4khz, duty=128/(2 256)=25%. if the duty value defned by the ccra register is equal to or greater than the period va lue, then the pwm output duty is 100%. ? 16-bit stm, pwm mode, edge-aligned mode, stdpx=1 ccrp 1~255 0 pe?iod ccra duty ccrp ?5? ?553? the pwm output period is determined by the ccra register value together with the stm clock while the pwm duty cycle is defned by the ccrp register value except when the ccrp value is equal to 0.
rev. 1.00 ?4 ?ove??e? 1?? ?01? rev. 1.00 ?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counte? value ccrp ccra sto? stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin (stoc=1) ti?e counte? clea?ed ?y ccrp pause resu?e counte? stop if sto? ?it low counte? reset when sto? ?etu?ns high stdpx = 0; stm [1:0] = 10 pwm duty cycle set ?y ccra pwm ?esu?es ope?ation output cont?olled ?y othe? pin-sha?ed function output inve?ts when stpol = 1 pwm pe?iod set ?y ccrp stm o/p pin (stoc=0) pwm output mode C stdpx=0 note: 1. here stdpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when stio[1:0]=00 or 01 4. the stcclr bit has no infuence on pwm operation
rev. 1.00 ?4 ?ove??e? 1?? ?01? rev. 1.00 ?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counte? value ccrp ccra sto? stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin (stoc=1) ti?e counte? clea?ed ?y ccra pause resu?e counte? stop if sto? ?it low stdpx = 1; stm [1:0] = 10 pwm duty cycle set ?y ccrp pwm ?esu?es ope?ation output cont?olled ?y othe? pin-sha?ed function output inve?ts when stpol = 1 pwm pe?iod set ?y ccra stm o/p pin (stoc=0) counte? reset when sto? ?etu?ns high pwm output mode C stdpx=1 note: 1. here stdpx=1 C counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when stio[1:0]=00 or 01 4. the stcclr bit has no infuence on pwm operation
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu single pulse mode to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 10 respectively and also the stio1 and stio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the stm output pin. the trigger for the pulse output leading edge is a low to high transition of the ston bit, which can be implemented using the application program. however in the single pulse mode, the ston bit can also be made to automatically change from low to high using the external stck pin, which will in turn initiate the single pulse output. when the ston bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the ston bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the ston bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. s/w co??and set sto? o? stck pin t?ansition t?ailing edge s/w co??and clr sto? o? ccra co?pa?e match stp output pin pulse width = ccra value leading edge sto? ?it 0 1 sto? ?it 1 0 single pulse generation
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counte? value ccrp ccra sto? stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin (stoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when sto? ?etu?ns high stm [1:0] = 10 ; stio [1:0] = 11 pulse width set ?y ccra output inve?ts when stpol = 1 ?o ccrp inte??upts gene?ated stm o/p pin (stoc=0) stck pin softwa?e t?igge? clea?ed ?y ccra ?atch stck pin t?igge? auto. set ?y stck pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra match 2. ccrp is not used 3. the pulse is triggered by the stck pin or setting the ston bit high 4. in the single pulse mode, stio [1:0] must be set to "11" and cannot be changed. however a compare match from comparator a will also automatically clear the ston bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a stm interrupt. the counter can only be reset back to zero when the ston bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the stcclr and stdpx bits are not used in this mode.
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu capture input mode to select this mode bits stm1 and stm0 in the stmc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurement. the external signal is supplied on the stp, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the stio1 and stio0 bits in the stmc1 register. the counter is started when the ston bit changes from low to high which is initiated using the application program. when the required edge transition appears on the stp the present value in the counter will be latched into the ccra registers and a stm interrupt generated. irrespective of what events occur on the stp the counter will continue to free run until the ston bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a stm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the stio1 and stio0 bits can select the active trigger edge on the stp to be a rising edge, falling edge or both edge types. if the stio1 and stio0 bits are both set high, then no capture operation will take place irrespective of what happens on the stp, however it must be noted that the counter will continue to run. the stcclr and stdpx bits are not used in this mode.
rev. 1.00 ?? ?ove??e? 1?? ?01? rev. 1.00 ?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counter value yy ccrp ston stpau ccrp int. flag stmpf ccra int. flag stmaf ccra value time counter cleared by ccrp pause resume counter reset stm [1:0] = 01 stm capture pin stp xx counter stop stio [1:0] value xx yy xx yy active edge active edge active edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disable capture capture input mode note: 1. stm[1:0]=01 and active edge set by the stio[1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. the stcclr and stdpx bits are not used 4. no output function C stoc and stpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.00 90 ?ove??e? 1?? ?01? rev. 1.00 91 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu periodic type tm C ptm the periodic type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. f sys f sys /4 f h /?4 f h /1? f tbc ptck 000 001 010 011 100 101 110 111 ptck?~ptck0 10-?it count-up counte? 10-?it co?pa?ato? p ccrp ?0~?9 ?0~?9 10-?it co?pa?ato? a pto? ptpau co?pa?ato? a match co?pa?ato? p match counte? clea? 0 1 output cont?ol pola?ity cont?ol ptp pin input/output ptp ptoc ptm1? ptm0 ptio1? ptio0 ptmaf inte??upt ptmpf inte??upt ptpol ccra ptcclr edge detecto? ptio1? ptio0 f h 1 0 ptcapts periodic type tm block diagram periodic tm operation the periodic type tm core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 10-bit wide. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the pton bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a ptm interrupt signal will also usually be generated. the periodic type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control more than one output pin. all operating setup conditions are selected using relevant internal registers. periodic type tm register description overall operation of the periodic type tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra value and ccrp value. the remaining two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 ptmc0 ptpau ptck? ptck1 ptck0 pto ? ptmc1 ptm1 ptm0 ptio1 ptio0 ptoc ptpol ptcapts ptcclr ptmdl d7 d? d5 d4 d3 d? d1 d0 ptmdh d9 d? ptmal d7 d? d5 d4 d3 d? d1 d0 ptmah d9 d? ptmrpl d7 d? d5 d4 d3 d? d1 d0 ptmrph d9 d? 10-bit periodic tm register list
rev. 1.00 90 ?ove??e? 1?? ?01? rev. 1.00 91 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu p tmc0 register bit 7 6 5 4 3 2 1 0 ?a?e ptpau ptck? ptck1 ptck0 pto ? r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 p tpau : p tm counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the ptm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 p tck2~ptck0 : select ptm counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f tbc 10 1: f 110: ptck rising edge clock 111: ptck falling edge clock these three bi ts are used to select the clock source for the ptm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, while f and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 p ton : p tm counter on/off control 0: off 1: on this bit controls the overall on/off function of the ptm. setting the bit high enables the counter to run, clearing the bit disables the ptm. clearing this bit to zero will stop the counter from counting and turn off the ptm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the ptm is in the compare match output mode , pwm output mode or single pulse output mode then the ptm output pin will be reset to its initial condition, as specifed by the ptoc bit, when the pton bit changes from low to high. bit 2~0 unimplemented, read as "0" p tmc1 register bit 7 6 5 4 3 2 1 0 ?a?e ptm1 ptm0 ptio1 ptio0 ptoc ptpol ptcapts ptcclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ptm1~ptm0 : select ptm operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the ptm. to ensure reliable operation the ptm should be switched off before any changes are made to the ptm1 and ptm0 bits. in the timer/counter mode, the ptm output pin control must be disabled.
rev. 1.00 9? ?ove??e? 1?? ?01? rev. 1.00 93 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 5~4 p tio1~ptio0 : select ptm external pin function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of ptp or ptck 01: input capture at falling edge of ptp or ptck 10: input capture at falling/rising edge of ptp or ptck 11: input capture disabled timer/counter mode unused these two bits are used to determine how the ptm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the ptm is running. in the compare match output mode, the ptio1 and ptio0 bits determine how the ptm output pin changes state when a compare match occurs from the comparator a. the ptm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the ptm output pin should be setup using the ptoc bit in the ptmc1 register. note that the output level requested by the ptio1 and ptio0 bits must be different from the initial value setup using the ptoc bit otherwise no change will occur on the ptm output pin when a compare match occurs. after the ptm output pin changes state, it can be reset to its initial level by changing the level of the pton bit from low to high. in the pwm mode, the ptio1 and ptio0 bits determine how the ptm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the ptio1 and ptio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the ptio1 and ptio0 bits are changed when the ptm is running. bit 3 p toc : ptm p tp output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the ptm output pin. its operation depends upon whether ptm is being used in the compare match output mode or in the pwm mode/single pulse output mode . it has no effect if the ptm is in the timer/counter mode. in the compare match output mode it determines the logic level of the ptm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 p tpol : ptm p tp output polarity control 0: non-invert 1: invert this bit controls the polarity of the ptp output pin. when the bit is set high the ptm output pin will be inverted and not inverted when the bit is zero. it has no effect if the ptm is in the timer/counter mode.
rev. 1.00 9? ?ove??e? 1?? ?01? rev. 1.00 93 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 1 p tcapts : p tm capture trigger source selection 0: from ptp pin 1: from ptck pin bit 0 p tcclr : select ptm counter clear condition 0: comparator p match 1: comparator a match this bit is used to select the method which clears the counter. remember that the periodic tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the ptcclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ptcclr bit is not used in the pwm mode, single pulse or capture input mode. p tmdl register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : p tm counter low byte register bit 7 ~ bit 0 ptm 10-bit counter bit 7 ~ bit 0 ptmdh register bit 7 6 5 4 3 2 1 0 ?a?e d9 d? r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : ptm counter high byte register bit 1 ~ bit 0 ptm 10-bit counter bit 9 ~ bit 8 p tmal register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : p tm ccra low byte register bit 7 ~ bit 0 ptm 10-bit ccra bit 7 ~ bit 0 p tmah register bit 7 6 5 4 3 2 1 0 ?a?e d9 d? r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : ptm ccra high byte register bit 1 ~ bit 0 ptm 10-bit ccra bit 9 ~ bit 8
rev. 1.00 94 ?ove??e? 1?? ?01? rev. 1.00 95 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ptmrpl register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : p tm ccrp low byte register bit 7 ~ bit 0 ptm 10-bit ccrp bit 7 ~ bit 0 p tm rp h register bit 7 6 5 4 3 2 1 0 ?a?e d9 d? r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : ptm ccrp high byte register bit 1 ~ bit 0 ptm 10-bit ccrp bit 9 ~ bit 8 periodic type tm operating modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the ptm1 and ptm0 bits in the ptmc1 register. compare output mode to select this mode, bits ptm1 and ptm0 in the ptmc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the ptcclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both ptmaf and ptmpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the ptcclr bit in the ptmc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the ptmaf interrupt request fag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ptcclr is high no ptmpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be cleared to zero. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the ptmaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the ptm output pin, will change state. the ptm output pin condition however only changes state when a ptmaf interrupt request fag is generated after a compare match occurs from comparator a. the ptmpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the ptm output pin. the way in which the ptm output pin changes state are determined by the condition of the ptio1 and ptio0 bits in the ptmc1 register. the ptm output pin can be selected using the ptio1 and ptio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the ptm output pin, which is setup after the pton bit changes from low to high, is setup using the ptoc bit. note that if the ptio1 and ptio0 bits are zero then no pin change will take place.
rev. 1.00 94 ?ove??e? 1?? ?01? rev. 1.00 95 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counte? value 0x3ff ccrp ccra pto? ptpau ptpol ccrp int. flag ptmpf ccra int. flag ptmaf ptm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? clea?ed ?y ccrp value pause resu?e stop counte? resta?t ptcclr = 0; ptm [1:0] = 00 output pin set to initial level low if ptoc=0 output toggle with ptmaf flag ?ote ptio [1:0] = 10 active high output select he?e ptio [1:0] = 11 toggle output select output not affected ?y ptmaf flag. re?ains high until ?eset ?y pto? ?it output pin reset to initial value output cont?olled ?y othe? pin-sha?ed function output inve?ts when ptpol is high compare match output mode C ptcclr=0 note: 1. with ptcclr=0 a comparator p match will clear the counter 2. the tm output pin is controlled only by the ptmaf fag 3. the output pin is reset to its initial state by a pton bit rising edge
rev. 1.00 9? ?ove??e? 1?? ?01? rev. 1.00 97 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counte? value 0x3ff ccrp ccra pto? ptpau ptpol ccrp int. flag ptmpf ccra int. flag ptmaf ptm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? clea?ed ?y ccra value pause resu?e stop counte? resta?t ptcclr = 1; ptm [1:0] = 00 output pin set to initial level low if ptoc=0 output toggle with ptmaf flag ?ote ptio [1:0] = 10 active high output select he?e ptio [1:0] = 11 toggle output select output not affected ?y ptmaf flag. re?ains high until ?eset ?y pto? ?it output pin reset to initial value output cont?olled ?y othe? pin-sha?ed function output inve?ts when ptpol is high ptmpf not gene?ated ?o ptmaf flag gene?ated on ccra ove?flow output does not change compare match output mode C ptcclr=1 note: 1. with ptcclr=1 a comparator a match will clear the counter 2. the tm output pin is controlled only by the ptmaf fag 3. the output pin is reset to its initial state by a pton bit rising edge 4. a ptmpf fag is not generated when ptcclr=1
rev. 1.00 9? ?ove??e? 1?? ?01? rev. 1.00 97 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu timer/counter mode to select this mode, bits ptm1 and ptm0 in the ptmc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits ptm1 and ptm0 in the ptmc1 register should be set to 10 respectively. the pwm function within the ptm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the ptm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm output mode, the ptcclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the ptoc bit in the ptmc1 register is used to select the required polarity of the pwm waveform while the two ptio1 and ptio0 bits are used to enable the pwm output or to force the ptm output pin to a fxed high or low level. the ptpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit ptm, pwm mode, edge-aligned mode ccrp 1~1023 0 pe?iod 1~10?3 10?4 duty ccra if f sys =8mhz, ptm clock source select f sys /4, ccrp=512 and ccra=128, the ptm pwm output frequency=(f sys /4)/512=f sys /2048=4khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.00 9? ?ove??e? 1?? ?01? rev. 1.00 99 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counte? value ccrp ccra pto? ptpau ptpol ccrp int. flag ptmpf ccra int. flag ptmaf ptm o/p pin (ptoc=1) ti?e counte? clea?ed ?y ccrp pause resu?e counte? stop if pto? ?it low counte? reset when pto? ?etu?ns high ptm [1:0] = 10 pwm duty cycle set ?y ccra pwm ?esu?es ope?ation output cont?olled ?y othe? pin-sha?ed function output inve?ts when ptpol = 1 pwm pe?iod set ?y ccrp ptm o/p pin (ptoc=0) pwm output mode note: 1. counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when ptio [1:0]=00 or 01 4. the ptcclr bit has no infuence on pwm operation
rev. 1.00 9? ?ove??e? 1?? ?01? rev. 1.00 99 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu single pulse mode to select this mode, bits ptm1 and ptm0 in the ptmc1 register should be set to 10 respectively and also the ptio1 and ptio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the ptm output pin. the trigger for the pulse output leading edge is a low to high transition of the pton bit, which can be implemented using the application program. however in the single pulse mode, the pton bit can also be made to automatically change from low to high using the external ptck pin, which will in turn initiate the single pulse output. when the pton bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the pton bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the pton bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the pton bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a ptm interrupt. the counter can only be reset back to zero when the pton bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the ptcclr bit is not used in this mode. pto? ?it 0 1 s/w co??and set pto? o? ptck pin t?ansition pto? ?it 1 0 ccra t?ailing edge s/w co??and clr pto? o? ccra co?pa?e match ptp output pin pulse width = ccra value ccra leading edge single pulse generation
rev. 1.00 100 ?ove??e? 1?? ?01? rev. 1.00 101 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counte? value ccrp ccra pto? ptpau ptpol ccrp int. flag ptmpf ccra int. flag ptmaf ptm o/p pin (ptoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when pto? ?etu?ns high ptm[1:0] = 10 ; ptio[1:0] = 11 pulse width set ?y ccra output inve?ts when ptpol = 1 ?o ccrp inte??upts gene?ated ptm o/p pin (ptoc=0) ptck pin softwa?e t?igge? clea?ed ?y ccra ?atch ptck pin t?igge? auto. set ?y ptck pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the ptck pin or by setting the pton bit high 4. a ptck pin active edge will automatically set the pton bit high 5. in the single pulse mode, ptio [1:0] must be set to "11" and cannot be changed.
rev. 1.00 100 ?ove??e? 1?? ?01? rev. 1.00 101 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu capture input mode to select this mode bits ptm1 and ptm0 in the ptmc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the ptp or ptck pin which is selected using the ptcapts bit in the ptmc1 register. the input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the ptio1 and ptio0 bits in the ptmc1 register. the counter is started when the pton bit changes from low to high which is initiated using the application program. when the required edge transition appears on the ptp or ptck pin the present value in the counter will be latched into the ccra registers and a ptm interrupt generated. irrespective of what events occur on the ptp or ptck pin, the counter will continue to free run until the pton bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a ptm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the ptio1 and ptio0 bits can select the active trigger edge on the ptp or ptck pin to be a rising edge, falling edge or both edge types. if the ptio1 and ptio0 bits are both set high, then no capture operation will take place irrespective of what happens on the ptp or ptck pin, however it must be noted that the counter will continue to run. as the ptp or ptck pin is pin shared with other functions, care must be taken if the ptm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the ptcclr, ptoc and ptpol bits are not used in this mode.
rev. 1.00 10? ?ove??e? 1?? ?01? rev. 1.00 103 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu counte? value yy ccrp pto? ptpau ccrp int. flag ptmpf ccra int. flag ptmaf ccra value ti?e counte? clea?ed ?y ccrp pause resu?e counte? reset ptm [1:0] = 01 ptm captu?e pin ptp o? ptck xx counte? stop ptio [1:0] value xx yy xx yy active edge active edge active edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode note: 1. ptm [1:0]=01 and active edge set by the ptio [1:0] bits 2. a ptm capture input pin active edge transfers the counter value to ccra 3. ptcclr bit not used 4. no output function C ptoc and ptpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.00 10? ?ove??e? 1?? ?01? rev. 1.00 103 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d converter overview this device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. it also can convert the internal signals of the over current protection 0 or over current protection 1 opa output signal into a 12-bit digital value. the external or internal analog signal to be converted is determined by the acs3 ~ acs 0 bits. when the external analog signal channel, an8, an10 or an11, is to be converted, the sws0 or sws1 register bits together with the acs3~acs0 bits should be properly confgured to select the required input signals. more detailed information about the a/d input signal is described in the "a/d converter control registers" and "a/d converter input signals" sections respectively. external input channels internal signals channel select bits a?0~a? 11 a?1? : ocp0 opa output a? 13:ocp1 opa output acs3~acs0 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers. ouvp0_r0 ouvp0_r1 an10sw_0 an10sw_1 ouvp0s1 ouvp0s0 ouvp0_in ouvp1_r0 ouvp1_r1 an11sw_ 0 an 11sw _1 ouvp1s 1 ouvp1s0 ouvp1_in advbgen v dd savrs[ 1: 0 ] op amp + - advbg( 1. 2v ) v ri v r r 1 r1 advbgen 12 bits saradc an10/ ouvp0 an11/ ouvp1 ocp 1ao ocp 0ao an11sw an11sw an 10 sw an 10 sw acs[ 3: 0] batv _r 1 batv _r2 batvs1 batvs0 an0 an7 an8/ batv an9 acs[ 3: 0 ] pin- shared registers start adbz adcen v ss a/ d clock 2 n ( n=0~7) f sys sacks [ 2:0] v dd adcen sadol sadoh a/ d converter reference voltage a/d data registers adrfs savrs[ 1: 0] vref_r vref v dd vrefsw acs[ 3: 0] an10 an11 an 8 an12 an13 unit gain buffer advbgen v r o note: the unite-gain buffer output v ro can drive the ocpn, ovpn and uvpn dac. a/d converter structure
rev. 1.00 104 ?ove??e? 1?? ?01? rev. 1.00 105 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu a/d converter register description overall operation of the a/d converter is controlled using several registers. a read only register pair exists to store the a/d converter data 12-bit value. the remaining two registers are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 sadol(adrfs=0) d3 d? d1 d0 sadol(adrfs=1) d7 d? d5 d4 d3 d? d1 d0 sadoh(adrfs=0) d11 d10 d9 d? d7 d? d5 d4 sadoh(adrfs=1) d11 d10 d9 d? sadc0 start adbz adce? adrfs acs3 acs? acs1 acs0 sadc1 advbge? savrs1 savrs0 sacks? sacks1 sacks0 sws0 vrefsw batvs1 batvs0 a?10sw ouvp0s1 ouvp0s0 sws1 a? 11sw ouvp1s1 ouvp1s0 a/d converter register list a/d converter data registers as this device contains an internal 12-bit a/d converter, it requires two data registers to store the converted value. these are a high byte register, known as sadoh, and a low byte register, known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the sadc0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. note that a/d data registers contents will be unchanged if the a/d converter is disabled. adrfs sadoh sadol 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d? d7 d? d5 d4 d3 d? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d? d7 d? d5 d4 d3 d? d1 d0 a/d data registers a/d converter control registers to control the function and operation of the a/d converter, two control registers known as sadc0 and sadc1 and two switch control registers, sws0 and sws1, are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter busy status. as the device contains only one actual analog to digital converter hardware circuit, each of the external or internal analog signal inputs must be routed to the converter. the acs3~acs0 bits in the sadc0 register are used to determine which input signal is selected to be converted. the an8, an10 and an11 input channel each has an integrated voltage divider circuit can be connected or disconnected using the sws0 and sws1 registers controlled internal analog switches. the relevant pin-shared function selection bits determine which pins on i/o ports are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin- shared function will be removed. in addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an a/d converter input.
rev. 1.00 104 ?ove??e? 1?? ?01? rev. 1.00 105 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ? s adc0 register bit 7 6 5 4 3 2 1 0 ?a?e start adbz adce? adrfs acs3 acs? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 adbz : a/d converter busy fag 0: no a/d conversion is in progress 1: a/d conversion is in progress this read only fag is used to indicate whether the a/d conversion is in progress or not. when the start bit is set from low to high and then to low again, the adbz fag will be set to 1 to indicate that the a/d conversion is initiated. the adbz fag will be cleared to 0 after the a/d conversion is complete. bit 5 adcen : a/d converter function enable control 0: disable 1: enable this bit controls the a/d internal function. this bit should be set to one to enable the a/d converter. if the bit is set low, then the a/d converter will be switched off reducing the device power consumption. when the a/d converter function is disabled, the contents of the a/d data register pair known as sadoh and sadol will be unchanged. bit 4 adrfs : a/d converter data format select 0: a/d converter data format sadoh=d[11:4]; sadol=d[3:0] 1: a/d converter data format sadoh=d[11:8]; sadol=d[7:0] this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~0 acs3~acs0 : a/d converter input channel select 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 000: an 001: an 9 010: an 10 011: an 100: an12 (from ocp0 opa output, ocp0ao) 1101: an13 (from ocp1 opa output, ocp1ao) 1110: an0 1111: an0
rev. 1.00 10? ?ove??e? 1?? ?01? rev. 1.00 107 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ? s adc1 register bit 7 6 5 4 3 2 1 0 ?a?e advbge? savrs1 savrs0 sacks? sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 advbgen : internal 1.2v bandgap and opa (gain=2) and unit-gain buffer enable control 0: disable 1: enable this bit controls the a/d converter internal 1.2v bandgap and opa on/off. the 1.2v bandgap voltage can be amplifed by 2 times via the internal opa. then a 2.4v reference voltage v r can be obtained. this bit also controls the enable of the internal unit-gain buffer which drivers the ocpn, ovpn and uvpn d/a converters. so if one of the functions above is used, this bit should be set high at frst. bit 4~3 savrs1~savrs0 : a/d converter reference voltage adc_v ref select 00: internal a/d converter power, v 01: from external vref pin 0 : internal v r - 2.4v opa(gain=2)output voltage : internal a/d converter power, v hese two bits are used to selecte the a/d converter reference voltage. note that when the internal 2.4v v r is selected as the a/d converter reference voltage, the advbgen bit should be set high to turn on the 1.2v bandgap and opa function. bit 2~0 sacks2~sacks0 : a/d conversion clock select 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: f /128 ? sws0 register bit 7 6 5 4 3 2 1 0 ?a?e vrefsw batvs1 batvs0 a?10sw ouvp0s1 ouvp0s0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 vrefsw : internal 1k resistor switch vrefsw control 0: switch off, vref_r resistor is not connected to vdd 1: switch on, vref_r resistor is connected to vdd this bit determines the on/off control for the switch between the vref_r resistor and the v voltage. but only when the savrs[1:0] bits value is "01b", selecting the vref pin as the a/d converter reference voltage source, and then set this vrefsw bit high, can the vref_r resistor be enabled. otherwise this switch is always off. bit 4 batvs1 : internal bypass switch batvs1 control 0: switch off 1: switch on this bit controls the switch batvs1 on/off. but only when the acs[3:0] bits value is "1000b", selecting the an8 as the a/d converter input signal channel, and then set this batvs1 bit high, can the switch be on. otherwise this switch is always off.
rev. 1.00 10? ?ove??e? 1?? ?01? rev. 1.00 107 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 3 batvs0 : internal divider resistor switch batvs0 control 0: switch off 1: switch on this bit controls the switch batvs0 on/off. but only when the acs[3:0] bits value is "1000b", selecting the an8 as the a/d converter input signal channel and the batvs1 bit is "0", turning off the batvs1 switch, and then set this batvs0 bit high, can the switch be on. otherwise this switch is always off. bit 2 an10sw : internal analog switches an10sw_0 and an10sw_1 control 0: an10sw_0 on, an10sw_1 off 1: an10sw_0 off, an10sw_1 on this bit controls the switches an10sw_0 and an10sw_1 on/off. but only when the acs[3:0] bits value is "1010b", selecting the an10 as the a/d converter input signal channel, is this bit setup valid. otherwise these two switches are both off. bit 1 ouvp0s1 : internal bypass switch ouvp0s1 control 0: switch off 1: switch on this bit controls the switch ouvp0s1 on/off. but only when the pin-shared function control bits pas1[1:0] value is "01b", selecting the an10 pin function, and then set this ouvp0s1 bit high, can the switch be on. otherwise this switch is always off. bit 0 ouvp0s0 : internal divider resistor switch ouvp0s0 control 0: switch off 1: switch on this bit controls the switch ouvp0s0 on/off. but only when the pin-shared function control bits pas1[1:0] value is "01b", selecting the an10 pin function and the ouvp0s1 bit is "0", turning off the ouvp0s1 switch, and then set this ouvp0s0 bit high, can the switch be on. otherwise this switch is always off. ? sws1 register bit 7 6 5 4 3 2 1 0 ?a?e a? 11sw ouvp1s1 ouvp1s0 r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as "0" bit 2 an11sw : internal analog switches an11sw_0 and an11sw_1 control 0: an11sw_0 on, an11sw_1 off 1: an11sw_0 off, an11sw_1 on this bit controls the switches an11sw_0 and an11sw_1 on/off. but only when the acs[3:0] bits value is "1011b", selecting the an11 as the a/d converter input signal channel, is this bit setup valid. otherwise these two switches are both off. bit 1 ouvp1s1 : internal bypass switch ouvp1s1 control 0: switch off 1: switch on this bit controls the switch ouvp1s1 on/off. but only when the pin-shared function control bits pas0[1:0] value is "01b", selecting the an11 pin function, and then set this ouvp1s1 bit high, can the switch be on. otherwise this switch is always off. bit 0 ouvp1s0 : internal divider resistor switch ouvp1s0 control 0: switch off 1: switch on this bit controls the switch ouvp1s0 on/off. but only when the pin-shared function control bits pas0[1:0] value is "01b", selecting the an11 pin function and the ouvp1s1 bit is "0", turning off the ouvp1s1 switch, and then set this ouvp1s0 bit high, can the switch be on. otherwise this switch is always off.
rev. 1.00 10? ?ove??e? 1?? ?01? rev. 1.00 109 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu a/d converter operation the start bit in the sadc0 register is used to start the a / d conversion. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. the adbz bit in the sadc0 register is used to indicate whether the analog to digital conversion process is in progress or not. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleared to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can poll the adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the sacks2~sacks0 bits in the sadc1 register. although the a/d clock source is determined by the system clock f sys and by bits sacks2~sacks0, there are some limitations on the maximum a/d clock source speed that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for system clock frequencies. for example, as the system clock operates at a frequency of 8 mhz, the sacks2~sacks0 bits should not be set to 000 , 0 01 or 111. doing so will give a/d clock periods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) sacks[2:0] = 000 (f sys ) sacks[2:0] = 001 (f sys /2) sacks[2:0] = 010 (f sys /4) sacks[2:0] = 011 (f sys /8) sacks[2:0] = 100 (f sys /16) sacks[2:0] = 101 (f sys /32) sacks[2:0] = 110 (f sys /64) sacks[2:0] = 111 (f sys /128) 1mhz 1s 2s 4s 8s 16s * 32s * 64s * 128s * ?mhz 500ns 1s 2s 4s 8s 16s * 32s * 64s * 4mhz ?50ns * 500ns 1s 2s 4s 8s 16s * 32s * ?mhz 1?5ns * ?50ns * 500ns 1s 2s 4s 8s 16s * a/d clock period examples controlling the power on/off function of the a/d converter circuitry is implemented using the adcen bit in the sadc0 register. this bit must be set high to power on the a/d converter. when the adcen bit is set high to power on the a/d converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs, if the adcen bit is high, then some power will still be consumed. in power conscious applications it is therefore recommended that the adcen is cleared to reduce power consumption when the a/d converter function is not being used.
rev. 1.00 10? ?ove??e? 1?? ?01? rev. 1.00 109 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu a/d converter reference voltages the reference voltage supply to the a/d converter can be supplied from the positive power supply pin, vdd, from an external reference source supplied on pin vref or from the opa 2.4v output voltage, v r . the desired selection is made using the savrs [ 1 :0] bits. when the savrs bit feld is set to "0 0 " or "11" , the a/d converter reference voltage will come from the vdd pin. w hen the savrs bit feld is set to "0 1 ", the a/d converter reference voltage will come from the vref pin. note that between the vref pin and the v dd , there is an internal 1k resistor which can be selected to connect or disconnect the v dd using the sws0 register vrefsw bit. when the savrs bit feld is set to "10", the reference voltage is selected from the 2.4v opa output voltage which is obtained by inputting the 1.2v bandgap voltage to the internal opa with a gain of 2. so when the 2.4v v r reference voltage is required, the advbgen bit should be also set to enable the opa function and the 1.2v bandgap. the analog input values must not be allowed to exceed the value of the selected reference voltage. a/d converter input signals all the external a/d analog channel input pins are pin-shared with the i/o pins as well as other functions. the corresponding pin-shared function control register bit for each a/d external input pin determine s whether the input pin are setup as a/d converter analog inputs or whether they have other functions. if the pin is setup to be as an a/d analog channel input, the original pin functions will be disabled. in this way, pins can be changed under program control to change their function between a/d inputs and other functions. all pull high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the port control register to enable the a/d input as when the pin-shared function control bits enable an a/d input, the status of the port control register will be overridden. there are two internal analog signals derived from the over current protection 0 and over current protection 1 analog output signal s , which can be connected to the a/d converter as the analog input signal by confguring the acs[3:0] bits. there are 12 external signal input channels, an0~an11. the acs3~acs0 bits can determine which external channel or internal signal is selected. if the an8, an10 or an11 input channel is selected, care must be taken that because each of them has a group of internal functional switched which are controlled by the sws0 and sws1 register bits, so the registers must also be correctly confgured to obtain the required input signal. conversion rate and timing diagram a complete a/d conversion contains two parts, data sampling and data conversion. the data sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. therefore a total of 16 a/d clock cycles for an external input a/d conversion which is defned as t adc are necessary. maximum single a/d conversion rate=a/d clock period / 16 the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16 t adck clock cycles where t adck is equal to the a/d clock period.
rev. 1.00 110 ?ove??e? 1?? ?01? rev. 1.00 111 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu adce? start adbz acs[3:0] off on off on t o??st t ads a/d sa?pling ti?e t ads a/d sa?pling ti?e sta?t of a/d conve?sion sta?t of a/ d conve?sion sta?t of a/d conve?sion end of a/d conve?sion end of a/d conve?sion t adc a/d conve?sion ti?e t adc a/d conve?sion ti?e t adc a/d conve?sion ti?e 0011b 0010b 0000b 0001b a/d channel switch a/d conversion timing summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits sacks2~sacks0 in the sadc1 register. ? step 2 enable the a/d by setting the adcen bit high in the sadc0 register. ? step 3 select which signal is to be connected to the internal a/d converter by correctly confguring the acs3~acs0 bits. ? step 4 select the reference voltage source by configuring the savrs1~savrs0 bits in the sadc1 register. ? step 5 select a/d converter output data format by setting the adrfs bit in the sadc0 register. ? step 6 if a/d conversion interrupt is used, the interrupt control registers must be correctly confgured to ensure the a/d interrupt function is active. as the a/d converter interrupt is contained within a multi-function interrupt, the associated multi-function interrupt enable bit, mfne, the master interrupt control bit, emi, and the a/d conversion interrupt control bit, ade, must all be set high in advance. ? step 7 the a/d conversion procedure can now be initialized by setting the start bit from low to high and then low again. ? step 8 if a/d conversion is in progress, the adbz fag will be high. after the a/d conversion process is completed, the adbz fag will go low and then the output data can be read from sadoh and sadol registers. if a/d converter interrupt is enabled and the stack is not full, data can be acquired by interrupt service program. another way to get a/d output data is to polling adbz fag. note: when checking for the end of the conversion process, if the method of polling the adbz bit in the sadc0 register is used, the interrupt enable step above can be omitted.
rev. 1.00 110 ?ove??e? 1?? ?01? rev. 1.00 111 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu programming considerations during microcontroller operations where the a/d converter is not being used, the a/d internal circuitry can be switched off to reduce power consumption, by clearing bit adcen to 0 in the sadc0 register. when this happens, the internal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d conversion function as the device contains a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the a/d converter reference voltage adc_ v ref which can be selected from v dd , vref pin input or opa output v r , this gives a single bit analog input value of adc_ v ref divided by 4096. 1 lsb=(adc_v ref ) 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value (adc_v ref ) 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the adc_ v ref level. fffh ffeh ffdh 03h 0?h 01h 0 1 ? 3 4093 4094 4095 409? adc_ v ref 409? analog input voltage a/d conversion result 1.5 lsb 0.5 lsb ideal a/d transfer function
rev. 1.00 11 ? ?ove??e? 1?? ?01? rev. 1.00 113 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu a/d conversion programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the sadc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an adbz polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov sadc1,a ; select f sys /8 as a/d clock set adcen mov a,01h ; setup pdps0 to confgure pin an0 mov pdps0,a mov a,20h mov sadc0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz adbz ; poll the sadc0 register adbz bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,sadol ; read low byte conversion result value mov sadol_buffer,a ; save result to user defned register mov a,sadoh ; read high byte conversion result value mov sadoh_buffer,a ; save result to user defned register : : jmp start_conversion ; start next a/d conversion
rev. 1.00 11 ? ?ove??e? 1?? ?01? rev. 1.00 113 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov sadc1,a ; select f sys /8 as a/d clock set adcen mov a,01h ; setup pdps0 to confgure pin an0 mov pdps0,a mov a,20h mov sadc0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag clr mf1f ; clear multi-function interrupt 1 request fag set ade ; enable adc interrupt set mf1e ; enable multi-function interrupt 1 set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,sadol ; read low byte conversion result value mov sadol_buffer,a ; save result to user defned register mov a,sadoh ; read high byte conversion result value mov sadoh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti
rev. 1.00 114 ?ove??e? 1?? ?01? rev. 1.00 115 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu high resolution pwm generator with auto-adjust control the device contains a multi feature fully integrated pwm generator which has complimentary outputs for maximum application fexibility. functional description the high resolution 8-bit pwm circuits include a pwm generator circuit, a delay lock loop circuit and pwm complementary outputs with dead time insertion. the device also provides the pwm duty adjusting control for high resolution pwm output. f hirc dll (1? phases) f dll dlle? dlllkf ?-?it pwm pwmn* p?escale? pwmnck[1:0] pwmno? pwmnp adjust ci?cuit ovp0i?t/ovp1i?t adjne? adjns uvpns[3:0] ovpns[3:0] adjndt uvp0i?t/uvp1i?t max/min duty co?pa?ato? adjnmaxh adjnmi?h adjnmi?l adjnmaxl buffe? n h.r pwm cont?ol mux dlln[3:0] co?ple?enta?y pwm cont?ol with dead ti?e pwmnh pwmnl dlle? h.r_pwmn* dtn[4:0] dlle? mux mux dllck* dt1ck* dt1sel[5:0]* dt?sel[5:0]* dt?ck* mux adjnsw pwmnd adjnbh adjnbl f/w w?ite ovpnl uvpnl outnh? outnl? outnh outnl dlllke? pwmnd note: 1. "*":means it is the internal signal name and not the special function register bit. dt1sel[5:0] and dt2sel[5:0] are calculated and selected automatically based on the dt[4:0]. dt1ck is the pwmnh dt reference signal dt2ck is the pwmnl dt reference signal dllck is the h.r_pwm reference signal 2. h.r=high resolution h.r pwm output block diagram (n=0 or 1)
rev. 1.00 114 ?ove??e? 1?? ?01? rev. 1.00 115 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu high resolution pwm registers the basic operation of the high resolution pwm is controlled using several registers. a pwm period register, pwmnp, exists to store the desired 8-bit pwm period value. the pwm duty value is stored in an 8-bit pwmnd register. the pwmn function control, pwmn counter clock selection, dll circuit and dead time duration is determined by the pwmnc register. the register dlln is used for the dll circuit phase selection. the dllc register is used for the dll circuit enable control and the losing lock protection control. there are also some registers used for the auto adjust pwm function. the register adjnc is to control the auto adjust function enable or disable, the pwmn duty adjust operation control and store the ouvpn comparator output status. the adjns register is to select the adjust steps when over voltage or under voltage condition occurs while the adjndt is to select the auto adjust function delay time after being triggered. the two register pairs of adjnmaxh & adjnmaxl and adjnminh & adjnminl are used to set the maximum and minimum duty data. the register pair of adjnbh& adjnbl is used to store the auto-adjust pwm buffer duty data. the remaining register of outpc0 is used for the pwmn output signals control. register name bit 7 6 5 4 3 2 1 0 pwmnp d7 d? d5 d4 d3 d? d1 d0 pwmnd d7 d? d5 d4 d3 d? d1 d0 pwmnc pwmnck1 pwmnck0 pwmno? dtn4 dtn3 dtn? dtn1 dtn0 dlln dlln3 dlln? dlln1 dlln0 dllc dlllke? dlle? dlllkf adjnc adjne? adjnv adjnsw ovpnl uvpnl adjns ovpns3 ovpns? ovpns1 ovpns0 uvpns3 uvpns? uvpns1 uvpns0 adjndt d5 d4 d3 d? d1 d0 adjnmaxh d11 d10 d9 d? adjnmaxl d7 d? d5 d4 d3 d? d1 d0 adjnmi?h d11 d10 d9 d? adjnmi?l d7 d? d5 d4 d3 d? d1 d0 adjnbh d11 d10 d9 d? adjnbl d7 d? d5 d4 d3 d? d1 d0 outpc0 out1hs out1ls out0hs out0ls out1h? out1l? out0h? out0l? high resolution pwm generator&auto-adjust register list (n=0 or 1) pwmnp register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : 8-bit pwm period register pwm period=pwmnp[7:0] +1
rev. 1.00 11 ? ?ove??e? 1?? ?01? rev. 1.00 117 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu pwmnd register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : 8-bit pwm duty register these registers, pwmnp and pwmnd, are used for 8-bit pwm period and duty control. the following should be noted during setup: 1. the pwmnd value should meet the condition: 1 pwmnd (pwmnp - 1) 2. pwmnd (min.)=1+dlln[3:0]-dtn[4:0] where dlln[3:0]=0000b, dtn[4:0]=11111b 3. pwmnd (max.)=pwmnp-1+dlln[3:0]-dtn[4:0] where dlln [3:0]=1111b, dtn[4:0]=00000b pwmnc register bit 7 6 5 4 3 2 1 0 ?a?e pwmnck1 pwmnck0 pwmno? dtn4 dtn3 dtn? dtn1 dtn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pwmnck1~pwmnck0 : pwm counter clock source selection 00: f hirc 01: f hirc /2 10: f hirc /4 11: f hirc /8 bit 5~4 pwmnon : pwmn function control bit 0: disable, pwm counter = 0 1: enable when clearing this bit to 0, the pwmn function is disabled. the outnh and outnl status is controlled by the outnhs and outnls bits of the outpc0 register. bit 4 ~0 dt n4~dtn 0 : pwm dead time selection 00000: dead time = t dll 0 ~ t dll 1 00001: dead time = t dll 2 ~ t dll 3 00010: dead time = t dll 4 ~ t dll 5 00011: dead time = t dll 6 ~ t dll 7 00100: dead time = t dll 8 ~ t dll 9 11101: dead time = t dll 58 ~ t dll 59 11110: dead time = t dll 60 ~ t dll 61 11111: dead time = t dll 62 ~ t dll 63 note: t dll = 1/(f hirc 16)
rev. 1.00 11 ? ?ove??e? 1?? ?01? rev. 1.00 117 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu dlln register bit 7 6 5 4 3 2 1 0 ?a?e dlln3 dlln? dlln1 dlln0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 dlln[3:0] : dll phase selection 0000: h.r_pwmn duty falling edge is fne-adjusted to be at the dll phase#0 rising edge 0001: h.r_pwmn duty falling edge is fne-adjusted to be at the dll phase#1 rising edge 0010: h.r_pwmn duty falling edge is fne-adjusted to be at the dll phase#2 rising edge 1110: h.r_pwmn duty falling edge is fne-adjusted to be at the dll phase#14 rising edge 1111: h.r_pwmn duty falling edge is fne-adjusted to be at the dll phase#15 rising edge bit 3~0 unimplemented, read as "0" dllc register bit 7 6 5 4 3 2 1 0 ?a?e dlllke? dlle? dlllkf r/w r/w r/w r/w por 0 0 0 bit 7 dlllken : dll circuit losing lock protection function control 0: disable 1: enable note: when dlllken=1 and dll function is enabled, if a losing lock condition occurs, the dlllkf bit is set high and the losing lock condition will be sovled by dll automatically. while when dlllken=0, the dlllkf bit is always zero even if a losing lock condition occurs, and the dll will not solve the condition. bit 6 dllen : dll and dead time function control bit 0: dll disabled and no dead time inserted 1: dll enabled and the dead time inserted which is decided by dtn[4:0] if this bit is cleared then the pwmnck[1:0] bits can be set to 00~11 by software and the h.r_pwmn=pwmn, no dead time is inserted. if set high, the hardware will set pwmnck[1:0] be 00 which cannot be changed, the pwmn will be fnely adjusted by the dll and then output the high resolution pwm output with dead time inserted. bit 5~1 unimplemented, read as "0" bit 0 dlllkf : dll circuit losing lock fag 0: no losing lock condition occurs 1: losing lock occurs this bit can be cleared to zero by software, but can not be set high by software. note: when dlllken=1 and dll function is enabled, if no losing lock condition occurs, the dlllkf bit is 0, if a losing lock condition occurs, the dlllkf bit is set high which can only be cleared by software. if dlllken=0, the dlllkf bit is always zero.
rev. 1.00 11 ? ?ove??e? 1?? ?01? rev. 1.00 119 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu adjndt register bit 7 6 5 4 3 2 1 0 ?a?e d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 d5~d0 : auto adjust pwmn delay time selection 000000: delay time=pwmn cycle 2 000001: delay time=pwmn cycle 4 000010: delay time=pwmn cycle 6 111111: delay time=pwmn cycle 128 delay time=(adjndt[5:0]+1) pwmn cycle 2 adjns register bit 7 6 5 4 3 2 1 0 ?a?e ovpns3 ovpns? ovpns1 ovpns0 uvpns3 uvpns? uvpns1 uvpns0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 ovpns[3:0] : ovpn auto adjust pwmn duty steps selection 0000: 0 step 0001: 1 step 1111: 15 steps bit 3~0 uvpns[3:0] : uvpn auto adjust pwmn duty steps selection 0000: 0 step 0001: 1 step 1111: 15 steps adjnc register bit 7 6 5 4 3 2 1 0 ?a?e adjne? adjnv adjnsw ovpnl uvpnl r/w r/w r/w r/w r r por 0 0 0 x x bit 7 adjnen : auto adjust pwm duty function control 0: disable 1: enable bit 6 adjnv : auto adjust pwmn duty action selection 0: ovpnl increase duty, uvpnl decrease duty 1: ovpnl decrease duty, uvpnl increase duty bit 5 adjnsw : pwmn duty adjustment by s/w auto adjust control 0: disable, write into buffer from pwmnd+dlln registers by f/w 1: enable, write into buffer by auto adjust system when the adjnen is cleared to zero, the auto adjust circuit is off, so this bit is always 0. when the adjnen bit is set high, the auto adjust circuit is on. then if the ovpnl or uvpnl is 1, this bit will be set to 1 automatically to trigger the auto adjust system to control the duty. when the auto duty adjustment is completed and if want to set the pwmn duty by f/w, then it needs to switch the adjnsw bit from 1 to 0. note that only when the ovpnl and uvpnl bits are equal to 0, can the bit be change from 1 to 0 successfully. bit 4 unimplemented, read as "0"
rev. 1.00 11 ? ?ove??e? 1?? ?01? rev. 1.00 119 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 3 ovpnl : ovpn comparator output status 0: output low (no over voltage occurs) 1: output high (over voltage occurs) bit 2 uvpnl : uvpn comparator output status 0: output low (no under voltage occurs) 1: output high(over voltage occurs) bit 1~0 unimplemented, read as "0" adjnmaxh & adjnmaxl registers register adjnmaxh adjnmaxl bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ?a?e d11 d10 d9 d? d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 0 0 0 0 " ": unimplemented, read as "0" d11~d8 : auto adjust pwmn maximum duty high byte d7~d0 : auto adjust pwmn maximum duty low byte d11~d4 is corresponding to the pwmnd [7:0], d3~d0 is corresponding to the dlln[3:0] bits adjnminh & adjnminl registers register bit adjnminh adjnminl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ?a?e d11 d10 d9 d? d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 0 0 0 0 " ": unimplemented, read as "0" d11~d8 : auto adjust pwmn minimum duty high byte d7~d0 : auto adjust pwmn minimum duty low byte d11~d4 is corresponding to the pwmnd [7:0], d3~d0 is corresponding to the dlln[3:0] bits adjnbh & adjnbl registers register adjnbh adjnbl bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ?a?e d11 d10 d9 d? d7 d? d5 d4 d3 d? d1 d0 r/w r r r r r r r r r r r r por 0 0 0 0 0 0 0 0 0 0 0 0 " ": unimplemented, read as "0" d11~d8 : auto adjust pwmn buffer duty high byte d7~d0 : auto adjust pwmn buffer duty low byte d11~d4 is corresponding to the pwmnd [7:0], d3~d0 is corresponding to the dlln[3:0] bits outpc0 register bit 7 6 5 4 3 2 1 0 ?a?e out1hs out1ls out0hs out0ls out1h? out1l? out0h? out0l? r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 out1hs : out1h status when an ocp/ouvp occurs or when the pwm is disabled 0: output 0 1: output1 bit 6 out1ls : out1l status when an ocp/ouvp occurs or when the pwm is disabled 0: output 0 1: output1
rev. 1.00 1?0 ?ove??e? 1?? ?01? rev. 1.00 1?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 5 out0hs : out0h status when an ocp/ouvp occurs or when the pwm is disabled 0: output 0 1: output1 bit 4 out0ls : out0l status when an ocp/ouvp occurs or when the pwm is disabled 0: output 0 1: output1 bit 3 out1hn : out1h signal inverting control 0: non-inverted 1: inverted bit 2 out1ln : out1l signal inverting control 0: non-inverted 1: inverted bit 1 out0hn : out0h signal inverting control 0: non-inverted 1: inverted bit 0 out0ln : out0l signal inverting control 0: non-inverted 1: inverted pwm generator the pwm signal generator is driven by the hirc clock and can generate pwmn signal, with a variable duty and period cycles by confguring the 8-bit pwmnp and pwmnd registers. the pwmn signal period is dependent upon the pwmn counter clock source which is set by the pwmnck[1:0] bits in the pwmnc register and determined by the pwmnp register. the pwmn signal duty is determined by the pwmd register content. pwmnp(old) pwmnd(old) pwmnd(?ew) pwmnp(?ew) ?-?it pwm pwmnd(?ew) pwmnp(?ew) ?ew pwm duty ?ew pwm pe?iod pwmn after the dlln, dtn[4:0], pwmnd and pwmnp register values are changed by software, then the new data will be updated by the f/w when the pwmn counter is cleared to zero. delay lock loop dll is an abbreviation for delay lock loop. the dll can generate 16 phase outputs within one hirc clock period. the 16 phase outputs are used to fne tune the pwmn signal output. the pwmn clock is f hirc , which means that the pwmn output duty resolution is 1/ f hirc . the pwmn signal passes through the dlln phase selection and pwmn control which is set by the dlln[3:0] bits in the dlln register circuit to output a fne-tuned pwmn signal, h.r_pwmn with the pwmn duty resolution increased by 4 bits.
rev. 1.00 1?0 ?ove??e? 1?? ?01? rev. 1.00 1?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu losing lock protection the device also provides the losing lock protection circuit which can be enabled by the dlllken bit. if the mcu is disturbed, a losing lock error that the phase time generated by the dll is 1.5 times of the normal phase time may occur. if the dlllken bit is high, the losing lock circuit is enabled and then the phase time will return normal in 30s. additionally the fag bit dlllkf which is 0 in normal operation will be set high to notify users that a losing lock error occurred. if the dlllken bit is not set high, the losing lock protection circuit is off. so after a losing lock condition occurs, the dll phase time cannot return normal automatically and the dlllkf fag is always 0. hirc dll #1 dll #? dll #3 hirc pwmn h.r_pwmn pwmnd[7:0]=5 dlln[3:0]=a h.r_pwmn dll #4 dll #5 dll #? dll #7 dll #? dll #9 dll #a dll #b dll #c dll #d dll #e dll #f dll #0 tdn = t pd + n * t hirc / 1? td1 = t pd + 1 * t hirc / 1?
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu auto-adjust circuit in order to increase the dc-dc response speed, the device provides an auto-adjust circuit together with the pwm generator. the following summarises the steps to implement the auto adjust function. step 1. clear the adjnen bit to zero to turn off the auto-adjust circuit for initialization: ? set the maximum/minimum duty by programming the12-bit adjnmaxh &adjnmaxl and adjnminh &adjnminl registers. note: 1 rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu co?ple?enta?y pwm output (with dead ti?e cont?ol) pwmnh h.r_pwmn dt dllne? dtn[4:0] a b c d a b c d dt dt dt dt pwmnl h.r_pwmn note: c and d are the complementary pwmn control with dead time circuitrys output signals.
rev. 1.00 1?4 ?ove??e? 1?? ?01? rev. 1.00 1?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu protection and inverting control although a dead time has been inserted into the h.r_pwm complementary pair signals to prevent excessive dc current, these two signals may also be in an inactive state resulting from some unpredictable reasons, such as malfunctions or electrical noise. the device provides a protection function to force the two signals to output inverting signals when the pwmnh or pwmnl signal is in an inactive state. the inverting control circuitry determines whether the signals are inverted or not using corresponding inverting control bit, outnhn or outnln bit, in the outpc0 register. outnh p?otection ci?cuit pwmnl outnh? outnl? pwmnh outnl ovp0i?t ouvp1pc uvp0i?t ovp1i?t uvp1i?t ouvp0pc ocppc the device also includes over current protection, over voltage protection and under voltage protection functions for the pwmn output signals which are described in the ocpn ocppc register and ouvpn section ouvpnpc register. the pwm output out0h/out0l, out1h/out1l can be forced as inactive state controlled by out0hs/out0ls, out1hs/out1ls bits in the outpc0 register for either ocpn, ovpn or uvpn occurs. the ocpn/ovpn/uvpn also generates interrupt to inform mcu. once ocpn/ovpn/uvpn disappears, the out0h/out0l, out1h/out1l will recover to send pwm output. details about the current and voltage protection functions refer to the "over current protection" and "over/under voltage protection" chapters. programming considerations the following steps show the read and write procedures: ? writing data to dlln/pwmnd ? step 1. write data to dlln C note that here data is only written to the 4-bit buffer. ? step 2. write data to pwmnd C here data is written directly to pwmnd register and simultaneously data is latched from the 4-bit buffer to the dlln register. ? reading data from dlln/pwmnd ? step 1. read data from pwmnd C here data is read directly from the pwmnd register and simultaneously data is latched from the dlln register into the 4-bit buffer. ? step 2. read data from dlln C this step reads data from the 4-bit buffer.
rev. 1.00 1?4 ?ove??e? 1?? ?01? rev. 1.00 1?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu over current protection the device includes the over current protection function which provides a protection mechanism for applications. to prevent the battery charge or load current from exceeding a specifc level, the current on the ocpn pin is converted to a relevant voltage level according to the current value using the ocpn operational amplifer. i t is then compared with a reference voltage generated by a n 8 -bit d/a converter. w hen an over current event occurs, an ocpn interrupt will be generated if the corresponding interrupt control is enabled. ocpn ocpnao ( to a/ d converter ) ocpnint ocpnchy s4 - + g n [ 2: 0] r2 opa + - 8 bit dac o cpnout debounce ocpno ocpndeb [ 2 : 0] r1 ( r1 = 4k ) ocpnen[ 1: 0] m u x ocpnda [ 7: 0] ocpnvrs [ 1: 0] v dd vr ef f sys s0 s1 s2 s 3 cmp v r o stop pwm output ocpn 0len, ocpn 0hen ocpn 1len, ocpn 1hen note: v ro is from the a/d converter unit gain buffer output and the ocpnao can be selected as the a/d converter input signals. over current protection circuit (n=0 or 1) over current protection operation t he illustrated ocpn circuit is used to prevent the input current from exceeding a reference level. t he current on the ocpn pin is converted to a voltage and then amplifed by the ocpn operational amplifier with a programmable gain from 1 to 50 selected by the gn2~gn0 bits in the ocpnc1 register. t his is known as a programmable gain amplifer or pga. t his pga can also be confgured to operate in the non-inverting, inverting or input offset calibration mode determined by the ocpnen1 and ocpnen0 bits in the ocpnc0 register. a fter the current is converted and amplifed to a specifc voltage level, it will be compared with a reference voltage provided by an 8-bit dac. the 8 -bit dac power can be v dd , v ro or v ref , selected by the ocpnvrs[1:0] bits in the ocpnc0 register . t he comparator output, ocpncout, will frst be fltered with a certain de-bounce time period selected by the ocpndeb2~ocpndeb0 bits in the ocpnc1 register. t hen a fltered ocpn digital comparator output, ocpno, is obtained to indicate whether an over current condition occurs or not. t he ocpno bit will be set to 1 if an over current condition occurs. o therwise, the ocpno bit is zero. once an over current event occurs, i.e., the converted voltage of the o c p n input current is greater than the reference voltage, the corresponding interrupt will be generated if the relevant interrupt control bit is enabled . the device provides over current protection control of the pwm output signals out0h/out0l, out1h/out1l which can be enabled by the corresponding ocppc register bits. if the protection control is enabled, these signal status is controlled by the out0hs/out0ls, out1hs/out1ls bits in the outpc0 register when an over current protection condition occurs. the ocpn also generates an interrupt to inform the mcu. once the over current condition is resolved the out0h/ out0l, out1h/out1l outputs will recover and continue to generate pwm signals. details about the outnh and outnl signal polarity and output control when ocpn occurs is described in the ocppc register description.
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu over current protection control registers overall operation of the over current protection is controlled using several registers. one register is used to provide the reference voltages for the over current protection circuit . there are two register s used to cancel out the operational amplifer and c omparator input offset. the two control registers are to control the o c p n function, d/a converter reference voltage select, pga gain select, comparator de - bounce time together with the hysteresis function. the remaining register of ocppc is used to control the whether the pwmn output signals out0h/out0l, out1h/out1l is forced into an inactive state when an ocpn condition occurs. register name bit 7 6 5 4 3 2 1 0 ocpnc0 ocpne?1 ocpne?0 ocpnvrs1 ocpnvrs0 ocpnchy ocpno ocpnc1 gn? gn1 gn0 ocpndeb? ocpndeb1 ocpndeb0 ocpnda d7 d? d5 d4 d3 d? d1 d0 ocpnocal ocpnoofm ocpnorsp ocpnoof5 ocpnoof4 ocpnoof3 ocpnoof? ocpnoof1 ocpnoof0 ocpnccal ocpncout ocpncofm ocpncrsp ocpncof4 ocpncof3 ocpncof? ocpncof1 ocpncof0 ocppc ocp11le ? ocp11he ? ocp10le? ocp10he? ocp01le? ocp01he? ocp00le? ocp00he? ocp n register list (n=0 or 1) ocp nc0 register bit 7 6 5 4 3 2 1 0 ?a?e ocpne?1 ocpne?0 ocpnvrs1 ocpnvrs0 ocpnchy ocpno r/w r/w r/w r/w r/w r/w r por 0 0 0 0 0 0 bit 7~6 ocpnen[1:0] : ocpn function operating mode selection 00: ocp n function is disable d, s1 and s3 on, s0 and s2 off 01: n on-invert ing mode , s0 and s3 on, s1 and s2 off 10: i nvert ing mode, s1 and s2 on, s0 and s3 off 11: calibration mode, s1 and s3 on, s0 and s2 off bit 5~4 ocpnvrs[1:0] : ocpn dac reference voltage selection 00: from v dd 01: from external vref pin 10: from internal v ro 11: from v dd note: when setting these bits to " 10 " to select the v ro as the ocpn dac reference voltage, care must be taken that as the v ro signal is from the unit gain buffer output, so the unit gain buffer must frst be enabled by setting the advbgen bit high. bit 3 ocpnchy : ocpn comparator hysteresis function control 0: disable 1: enable bit 2~1 unimplemented, read as "0" bit 0 ocpno : ocpn digital output bit 0: no over current condition occurs in the monitored source current 1: over current condition occurs in the monitored source current
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ocp nc1 register bit 7 6 5 4 3 2 1 0 ?a?e gn? gn1 gn0 ocpndeb? ocpndeb1 ocpndeb0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~3 gn[2:0] : r2/r1 ratio selection 000: unity gain buffer (non-inverting mode) or r2/r1= 1 (inverting mode) 001: r2/r1= 5 010: r2/r1= 10 011: r2/r1= 15 100: r2/r1= 20 101: r2/r1=3 0 110: r2/r1=4 0 111: r2/r1=5 0 these bits are used to select the r2/r1 ratio to obtain various gain values for inverting and non-inverting mode. the calculating formula of the ocpn pga gain for the inverting and non-inverting mode is described in the "input voltage range" section. bit 2~0 ocpndeb[2:0] : ocpn output flter debounce time selection 000: bypass, without debounce 001: ( 1~2 ) t deb 010: ( 3~4 ) t deb 011: ( 7~8 ) t deb 100: ( 15~16 ) t deb 101: ( 31~32 ) t deb 110: ( 63~64 ) t deb 111: ( 127~128 ) t deb note: t deb =1/f sys ocp nda register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ocpn dac output voltage control bits ocp dac output=(dac reference voltage/256) d[7:0] ocp n ocal register bit 7 6 5 4 3 2 1 0 ?a?e ocpnoofm ocpnorsp ocpnoof5 ocpnoof4 ocpnoof3 ocpnoof? ocpnoof1 ocpnoof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 0 bit 7 ocpnoofm : ocpn operational amplifer normal operation or input offset voltage cancellation mode selection 0: normal operation, i nput o ffset c alibration disabled 1: input offset calibration mode this bit is used to control the ocpn operational amplifier input offset calibration function. the ocpnen1 and ocpnen0 bits must first be set to "11" and then the ocpnoofm bit must be set to 1 followed by the ocpncofm bit being cleared to 0, then the operational amplifer input offset calibration mode will be enabled. refer to the "operational amplifer input offset calibration" section for the detailed offset calibration procedures.
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 6 ocpnorsp : ocpn operational amplifer input offset voltage calibration reference selection 0: select negative input as the reference input 1: select positive input as the reference input bit 5~0 ocpnoof[5:0] : ocpn operational amplifer input offset voltage calibration value this 6-bit field is used to perform the operational amplifier input offset calibration operation and the value for the ocpn operational amplifier input offset calibration can be restored into this bit field. more detailed information is described in the "operational amplifer input offset calibration" section. ocp n ccal register bit 7 6 5 4 3 2 1 0 ?a?e ocpncout ocpncofm ocpncrsp ocpncof4 ocpncof3 ocpncof? ocpncof1 ocpncof0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 ocpncout : ocp comparator output bit, positive logic (read only) 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage this bit is used to indicate whether the positive input voltage is greater than the negative input voltage when the ocpn operates in the input offset calibration mode. if the ocpncout is set to 1, the positive input voltage is greater than the negative input voltage. otherwise, the positive input voltage is less than the negative input voltage. bit 6 ocpncofm : ocpn comparator normal operation or input offset calibration mode selection 0: normal operation, i nput o ffset c alibration m ode d isabled 1: input offset calibration mode enabled this bit is used to control the ocpn comparator input offset calibration function. the ocpnen1 and ocpnen0 bits must frst be set to "11" and then the ocpncofm bit must be set to 1 followed by the ocpnoofm bit being cleared to 0, then the comparator input offset calibration mode will be enabled. refer to the "comparator input offset calibration" section for the detailed offset calibration procedures. bit 5 ocpncrsp : ocpn comparator input offset calibration reference input selection 0: select negative input as the reference input 1: select positive input as the reference input bit 4~0 ocpncof4~ocpncof0 : ocpn comparator input offset calibration value this 5-bit feld is used to perform the comparator input offset calibration operation and the value for the ocpn comparator input offset calibration can be restored into this bit feld. more detailed information is described in the "comparator input offset calibration" section. ocppc register bit 7 6 5 4 3 2 1 0 ?a?e ocp11le ? ocp11he ? ocp10le? ocp10he? ocp01le? ocp01he? ocp00le? ocp00he? r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ocp11len : out1l over current protection 1 enable control 0: disable 1: enable this bit is used to control the out1l signal output when an over current 1 condition occurs. if clear this bit to 0, the function is disabled. this means the out1l output will not be affected when ocp1 occurs. if set this bit high, the function is enabled. this means when an ocp1 condition occurs the out1l status is controlled by the out1ls bit in the outpc0 register.
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 6 ocp11hen : out1h over current protection 1 enable control 0: disable 1: enable this bit is used to control the out1h signal output when an over current 1 condition occurs. if clear this bit to 0, the function is disabled. this means the out1h output will not be affected when ocp1 occurs. if set this bit high, the function is enabled. this means when an ocp1 condition occurs the out1h status is controlled by the out1hs bit in the outpc0 register. bit 5 ocp10len : out0l over current protection 1 enable control 0: disable 1: enable this bit is used to control the out0l signal output when an over current 1 condition occurs. if clear this bit to 0, the function is disabled. this means the out0l output will not be affected when ocp1 occurs. if set this bit high, the function is enabled. this means when an ocp1 condition occurs the out0l status is controlled by the out0ls bit in the outpc0 register. bit 4 ocp10hen : out0h over current protection 1 enable control 0: disable 1: enable this bit is used to control the out0h signal output when an over current 1 condition occurs. if clear this bit to 0, the function is disabled. this means the out0h output will not be affected when ocp1 occurs. if set this bit high, the function is enabled. this means when an ocp1 condition occurs the out0h status is controlled by the out0hs bit in the outpc0 register. bit 3 ocp01len : out1l over current protection 0 enable control 0: disable 1: enable this bit is used to control the out1l signal output when an over current 0 condition occurs. if clear this bit to 0, the function is disabled. this means the out1l output will not be affected when ocp0 occurs. if set this bit high, the function is enabled. this means when an ocp0 condition occurs the out1l status is controlled by the out1ls bit in the outpc0 register. bit 2 ocp01hen : out1h over current protection 0 enable control 0: disable 1: enable this bit is used to control the out1h signal output when an over current 0 condition occurs. if clear this bit to 0, the function is disabled. this means the out1h output will not be affected when ocp0 occurs. if set this bit high, the function is enabled. this means when an ocp0 condition occurs the out1h status is controlled by the out1hs bit in the outpc0 register. bit 1 ocp00len : out0l over current protection 0 enable control 0: disable 1: enable this bit is used to control the out0l signal output when an over current 0 condition occurs. if clear this bit to 0, the function is disabled. this means the out0l output will not be affected when ocp0 occurs. if set this bit high, the function is enabled. this means when an ocp0 condition occurs the out0l status is controlled by the out0ls bit in the outpc0 register. bit 0 ocp00hen : out0h over current protection 0 enable control 0: disable 1: enable this bit is used to control the out0h signal output when an over current 0 condition occurs. if clear this bit to 0, the function is disabled. this means the out0h output will not be affected when ocp0 occurs. if set this bit high, the function is enabled. this means when an ocp0 condition occurs the out0h status is controlled by the out0hs bit in the outpc0 register.
rev. 1.00 130 ?ove??e? 1?? ?01? rev. 1.00 131 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu input voltage range t ogether with different pga operating modes, the input voltage on the ocpn pin can be positive or negative for flexible operation. t he pga output for the positive or negative input voltage is calculated based on different formulas and described by the following. ? for input voltages v in > 0, the pga operates in the non-inverting mode and the pga output is obtained using the formula below: v out = (1 + r 2 r 1 ) v in ? when the pga operates in the non-inverting mode by setting the ocpnen[1:0] to "01" with unity gain select by setting the gn[2:0] to "000", the pga will act as a unit-gain buffer whose output is equal to v in . v out = v in ? for input voltages 0 >v in >-0.2v, the pga operates in the inverting mode and the pga output is obtained using the formula below. note that if the input voltage is negative, it cannot be lower than -0.2v which will result in current leakage. v out = - r 2 r 1 v in ocpn opa and comparator offset calibration the ocpn circuit has four operating modes controlled by ocpnen[1:0], one of them is calibration mode. in calibration mode, operational amplifer and comparator offset can be calibrated. operational amplifer input offset calibration step 1. set ocpnen[1:0]=11, ocpnoofm=1 and ocpncofm=0, the ocpn will operate in the operational amplifer input offset calibration mode. step 2. set ocpnoof[5:0]=000000 and then read the ocpncout bit. step 3. increase the ocpnoof[5:0] value by 1 and then read the ocpncout bit. if the ocpncout bit state has not changed, then repeat step 3 until the ocpncout bit state has changed. if the ocpncout bit state has changed, record the ocpnoof value as v oos1 and then go to step 4. step 4. set ocpnoof[5:0]=111111 and read the ocpncout bit. step 5. decrease the ocpnoof[5:0] value by 1 and then read the ocpncout bit. if the ocpncout bit state has not changed, then repeat step 5 until the ocpncout bit state has changed. if the ocpncout bit state has changed, record the ocpnoof value as v oos2 and then go to step 6. step 6. restore the operational amplifer input offset calibration value v oos into the ocpnoof[5:0] bit feld. the offset calibration procedure is now fnished. where v oos = v oos1 + v oos2 2
rev. 1.00 130 ?ove??e? 1?? ?01? rev. 1.00 131 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu comparator input offset calibration step 1. set ocpnen[1:0]=11, ocpncofm=1 and ocpnoofm=0, the ocpn is now in the comparator input offset calibration mode. s4 is on (s4 is used for calibration mode, in normal mode operation, it is off). step 2. set ocpncof[4:0]=00000 and read the ocpncout bit. step 3. increase the ocpncof[4:0] value by 1 and then read the ocpncout bit. if the ocpncout bit state has not changed, then repeat step 3 until the ocpncout bit state has changed. if the ocpncout bit state has changed, record the ocpncof value as v cos1 and then go to step 4. step 4. set ocpncof[4:0]=11111 and then read the ocpncout bit. step 5. decrease the ocpncof[4:0] value by 1 and then read the ocpncout bit. if the ocpncout bit state has not changed, then repeat step 5 until the ocpncout bit state has changed. if the ocpncout bit state has changed, record the ocpncof value as v cos2 and then go to step 6. step 6. restore the comparator input offset calibration value v cos into the ocpncof[4:0] bit feld. the offset calibration procedure is now fnished. where v cos = v cos1 + v cos2 2
rev. 1.00 13? ?ove??e? 1?? ?01? rev. 1.00 133 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu over/under voltage protection the device includes the internal over/under voltage protection (ouvp) function which can be used for the application of battery charge/discharge. ouvp circuit operation the ouvp circuit is built-in with the over voltage protection (ovpn) and the under voltage protection (uvpn) functions. ovpnchy - + ovpno debounce ovpndeb [ 2: 0] f sys vref 8 bit dac m u x o v pnda[ 7: 0] o vpnvrs [ 1: 0] v dd ouvpn ovpnen uvpnchy - + uvpno debounce uvpndeb[ 2:0] uvpnen 8 bit dac m u x uvpnda[ 7: 0] uvpnvrs [ 1: 0] uvpnint uvpn cmp v ro ovpn cmp stop pwm output uvpn 0len , uvpn0hen uvpn 1len , uvpn1hen o vpnint stop pwm output ovpn 0len, ovpn 0hen ovpn 1len, ovpn 1hen v ro vref v dd note: v ro is from the a/d converter unit gain buffer over/under voltage protection block diagram (n=0 or 1) over voltage protection function to prevent the output voltage from exceeding the specifc voltage level, the ovpn input voltage is compared with a reference voltage generated by an 8-bit d/a converter. the 8-bit dac reference input signal range can come from v dd , v ro , or external vref pin which is selected by the ovpnvrs[1:0] bits. once the ovpn input voltage is greater than the reference voltage, the ovpno will change from "0" to "1". the ovpnint is the de-bounce version of ovpno and used to indicate that the source voltage coming from ouvpn input is over the specifcation or not. ovpno is defned as ovpn output and ovpnint is ovpn interrupt trigger. the comparator of the ovpn also has a hysteresis function controlled by ovpnchy bit. under voltage protection function to prevent the output voltage from being less than the specifc voltage, the uvpn input voltage is compared with a reference voltage generated by an 8-bit d/a converter. the 8-bit dac reference input signal range can come from v dd , v ro , or external vref pin which is selected by the uvpnvrs[1:0] bits. once the uvpn input voltage is lower than the reference voltage, the uvpno will change from "0" to "1". the uvpnint is the de-bounce version of uvpno and used to indicate that the source voltage coming from the ouvpn input is under the specifcation or not. uvpno is defned as uvpn output and uvpnint is uvpn interrupt trigger. the comparator of the uvpn also has a hysteresis function controlled by uvpnchy bit. the device provides over and under voltage protection control of the pwm output signals out0h/out0l, out1h/out1l which can be enabled by the corresponding ouvpnpc register bits. if the protection control is enabled, these signal status is controlled by the out0hs/out0ls, out1hs/out1ls bits in the outpc0 register for an over voltage or under voltage conditon occurs. the ovpn/uvpn also generates interrupt to inform mcu. once the ovpn/uvpn condition disappears, the out0h/out0l, out1h/ out1l outputs will continue to generate pwm signals. details about the outnh and outnl signal polarity and output control when ovpn or uvpn occurs is described in the ouvpnpc register description.
rev. 1.00 13? ?ove??e? 1?? ?01? rev. 1.00 133 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ouvpn register description the overall operation of the voltage protection and under voltage protection is controlled using several registers. register name bit 7 6 5 4 3 2 1 0 ovpnda d7 d? d5 d4 d3 d? d1 d0 uvpnda d7 d? d5 d4 d3 d? d1 d0 ouvpnc0 ovpne? ovpnchy ovpnvrs1 ovpnvrs0 ovpndeb1 ovpndeb0 ouvpnc1 uvpne? uvpnchy uvpnvrs1 uvpnvrs0 uvpndeb1 uvpndeb0 ouvpnc? ovpno ovpncofm ovpncrs ovpncof4 ovpncof3 ovpncof? ovpncof1 ovpncof0 ouvpnc3 uvpno uvpncofm uvpncrs uvpncof4 uvpncof3 uvpncof? uvpncof1 uvpncof0 ouvpnpc uvpn1le? uvpn1he? uvpn0le? uvpn0he? ovpn1le? ovpn1he? ovpn0le? ovpn0he? ouvp register list (n=0 or 1) ovpnda register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d[7:0] : data bits for ovpn dac output control ovpn dac output=(ovpn dac reference voltage) (ovpnda[7:0])/256 uvpnda register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d[7:0] : data bits for uvpn dac output control uvpn dac output=(uvpn dac reference voltage) (uvpnda[7:0])/256 ouvpnc0 register bit 7 6 5 4 3 2 1 0 ?a?e ovpne? ovpnchy ovpnvrs1 ovpnvrs0 ovpndeb1 ovpndeb0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 ovpnen : over voltage protection n function enable control 0: disable 1: enable if the ovpnen bit is cleared to 0, the over voltage protection n function is disabled and no power will be consumed. this results in the comparator and d/a converter of ovpn all being switched off. bit 4 ovpnchy : over voltage protection n comparator hysteresis enable control 0: disable 1: enable
rev. 1.00 134 ?ove??e? 1?? ?01? rev. 1.00 135 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 3~2 ovpnvrs[1:0] : ovp n dac reference voltage s elect ion 00: from v dd 01: from external vref pin 10: from internal v ro 11: from v dd note: when seting these bits to " 10 " to select the v ro as the ovpn dac reference voltage, care must be taken that as the v ro signal is from the unit gain buffer output, so the unit gain buffer must frst be enabled by setting the advbgen bit high. bit 1~0 ovpndeb[1:0] : over voltage protection n comparator debounce time selection 00: no debounce 01: (7~8) 1/f sys 10: (15~16) 1/f sys 11: (31~32) 1/f sys ouvpnc1 register bit 7 6 5 4 3 2 1 0 ?a?e uvpne? uvpnchy uvpnvrs1 uvpnvrs0 uvpndeb1 uvpndeb0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 uvpnen : under voltage protection n function enable control 0: disable 1: enable if the uvpnen bit is cleared to 0, the under voltage protection n function is disabled and no power will be consumed. this results in the comparator and d/a converter of uvpn all being switched off. bit 4 uvpnchy : under voltage protection n comparator hysteresis enable control 0: disable 1: enable bit 3~2 uvpnvrs[1:0] : u vp n dac reference voltage s elect ion 00: from v dd 01: from external vref pin 10: from internal v ro 11: from v dd note: when seting these bits to " 10 " to select the v ro as the uvpn dac reference voltage, care must be taken that as the v ro signal is from the unit gain buffer output, so the unit gain buffer must frst be enabled by setting the advbgen bit high. bit 1~0 uvpndeb[1:0] : under voltage protection n comparator debounce time selection 00: no debounce 01: (7~8) 1/f sys 10: (15~16) 1/f sys 11: (31~32) 1/f sys
rev. 1.00 134 ?ove??e? 1?? ?01? rev. 1.00 135 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ouvpnc2 register bit 7 6 5 4 3 2 1 0 ?a?e ovpno ovpncofm ovpncrs ovpncof4 ovpncof3 ovpncof? ovpncof1 ovpncof0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 ovpno : ovpn comparator output bit 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage bit 6 ovpncofm : ovpn comparator normal operation or input offset voltage cancellation mode selection bit 0: normal operation 1: input offset voltage calibration mode bit 5 ovpncrs : ovpn comparator input offset voltage calibration reference selection bit 0: input reference voltage comes from negative input 1: input reference voltage comes from positive input this bit is used to select that the reference input voltage comes from the ovpn d/a converter or external input. note that this bit is only available when the ovpn comparator input offset voltage calibration mode is selected by setting the ovpncofm bit to 1. bit 4~0 ovpncof[4:0] : ovpn comparator input offset voltage calibration control bits ouvpnc3 register bit 7 6 5 4 3 2 1 0 ?a?e uvpno uvpncofm uvpncrs uvpncof4 uvpncof3 uvpncof? uvpncof1 uvpncof0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 uvpno : uvpn comparator output bit 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage bit 6 uvpncofm : uvpn comparator normal operation or input offset voltage cancellation mode selection bit 0: normal operation 1: input offset voltage calibration mode bit 5 uvpncrs : uvpn comparator input offset voltage calibration reference selection bit 0: input reference voltage comes from negative input 1: input reference voltage comes from positive input this bit is used to select that the reference input voltage comes from the uvpn d/a converter or external input. note that this bit is only available when the uvpn comparator input offset voltage calibration mode is selected by setting the uvpncofm bit to 1. bit 4~0 uvpncof[4:0] : uvpn comparator input offset voltage calibration control bits
rev. 1.00 13? ?ove??e? 1?? ?01? rev. 1.00 137 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ouvpnpc register bit 7 6 5 4 3 2 1 0 ?a?e uvpn1le? uvpn1he? uvpn0le? uvpn0he? ovpn1le? ovpn1he? ovpn0le? ovpn0he? r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 uvpn1len : out1l under voltage protection n enable control 0: disable 1: enable this bit is used to control the out1l signal output when the under voltage protection condition occurs. if this bit is cleared to 0 the function is disabled. this means the out1l output will not be affected when uvpn occurs. if set this bit high, the function is enabled. this means when an uvpn condition occurs the out1l status is controlled by the out1ls bit in the outpc0 register. bit 6 uvpn1hen : out1h under voltage protection n enable control 0: disable 1: enable this bit is used to control the out1h signal output when the under voltage protection condition occurs. if clear this bit to 0, the function is disabled. this means the out1h output will not be affected when uvpn occurs. if set this bit high, the function is enabled. this means when an uvpn condition occurs the out1h status is controlled by the out1hs bit in the outpc0 register. bit 5 uvpn0len : out0l under voltage protection n enable control 0: disable 1: enable this bit is used to control the out0l signal output when the under voltage protection condition occurs. if clear this bit to 0, the function is disabled. this means the out0l output will not be affected when uvpn occurs. if set this bit high, the function is enabled. this means when an uvpn condition occurs the out0l status is controlled by the out0ls bit in the outpc0 register. bit 4 uvpn0hen : out0h under voltage protection n enable control 0: disable 1: enable this bit is used to control the out0h signal output when the under voltage protection condition occurs. if clear this bit to 0, the function is disabled. this means the out0h output will not be affected when uvpn occurs. if set this bit high, the function is enabled. this means when an uvpn condition occurs the out0h status is controlled by the out0hs bit in the outpc0 register. bit 3 ovpn1len : out1l over voltage protection n enable control 0: disable 1: enable this bit is used to control the out1l signal output when the over voltage protection condition occurs. if clear this bit to 0, the function is disabled. this means the out1l output will not be affected when ovpn occurs. if set this bit high, the function is enabled. this means when an ovpn condition occurs the out1l status is controlled by the out1ls bit in the outpc0 register. bit 2 ovpn1hen : out1h over voltage protection n enable control 0: disable 1: enable this bit is used to control the out1h signal output when the over voltage protection condition occurs. if clear this bit to 0, the function is disabled. this means the out1h output will not be affected when ovpn occurs. if set this bit high, the function is enabled. this means when an ovpn condition occurs the out1h status is controlled by the out1hs bit in the outpc0 register.
rev. 1.00 13? ?ove??e? 1?? ?01? rev. 1.00 137 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 1 ovpn0len : out0l over voltage protection n enable control 0: disable 1: enable this bit is used to control the out0l signal output when the over voltage protection condition occurs. if clear this bit to 0, the function is disabled. this means the out0l output will not be affected when ovpn occurs. if set this bit high, the function is enabled. this means when an ovpn condition occurs the out0l status is controlled by the out0ls bit in the outpc0 register. bit 0 ovpn0hen : out0h over voltage protection n enable control 0: disable 1: enable this bit is used to control the out0h signal output when the over voltage protection condition occurs. if clear this bit to 0, the function is disabled. this means the out0h output will not be affected when ovpn occurs. if set this bit high, the function is enabled. this means when an ovpn condition occurs the out0h status is controlled by the out0hs bit in the outpc0 register. ovpn and uvpn comparator offset calibration the ovpn and uvpn circuits provide comparator offset calibration function. before offset calibration, the hysteresis voltage should be zero by clearing the ovpnchy or uvpnchy bit to zero. as the ouvpn input pins are pin-shared with other functions, the ouvpn pin function must frst be setup as comparator input using the corresponding pin-shared function selection register bits. the following content are the steps for the ovpn or uvpn comparator calibration. ovpn comparator calibration: step1: set ovpncofm=1, ovpncrs=1, comparator is now under offset calibration mode. to make sure v os as minimize as possible after calibration, the input reference voltage in calibration should be the same as input dc operating voltage in normal mode operation. step2: set ovpncof[4:0]=00000 and then read the ovpno bit step3: increase the ovpncof[4:0] by 1 and then read the ovpno bit. if the ovpno bit state has not changed, then repeat step 3 until the ovpno bit state has changed. if the ovpno bit state has changed, record the ovpncof[4:0] value as v os1 and then go to step 4. step4: set ovpncof[4:0]=11111 and then read the ovpno bit step5: decrease the ovpncof[4:0] value by 1 and then read the ovpno bit. if the ovpno bit state has not changed, then repeat step 5 until the ovpno bit state has changed. if the ovpno bit state has changed, record the ovpncof[4:0] value as v os2 and then go to step 6. step6: restore the v os = v os1 + v os2 2 to ovpncof[4:0] bit feld, the calibration procedure is now fnished. if (v os1 + v os2 ) / 2 is not integral, discard the decimal. residue v os =v out - v in (1) uvpn comparator calibration: step1: set uvpncofm=1, uvpncrs=1, comparator is now under offset calibration mode. to make sure v os as minimize as possible after calibration, the input reference voltage in calibration should be the same as input dc operating voltage in normal mode operation. step2: set uvpncof[4:0]=00000 and then read the uvpno bit
rev. 1.00 13? ?ove??e? 1?? ?01? rev. 1.00 139 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu step3: increase the uvpncof[4:0] by 1 and then read the uvpno bit. if the uvpno bit state has not changed, then repeat step 3 until the uvpno bit state has changed. if the uvpno bit state has changed, record the uvpncof[4:0] value as v os1 and then go to step 4. step4: set uvpncof[4:0]=11111 and then read the uvpno bit step5: decrease the uvpncof[4:0] value by 1 and then read the uvpno bit. if the uvpno bit state has not changed, then repeat step 5 until the uvpno bit state has changed. if the uvpno bit state has changed, record the uvpncof[4:0] value as v os2 and then go to step 6. step6: restore the v os = v os1 + v os2 2 to uvpncof[4:0] bit feld, the calibration procedure is now fnished. if (v os1 + v os2 ) / 2 is not integral, discard the decimal. residue v os =v out - v in (2)
rev. 1.00 13? ?ove??e? 1?? ?01? rev. 1.00 139 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu usb auto detection the device includes three usb ports named d0+/d0-, d1+/d1- and d2+/d2- to implement the charge/discharge devices auto detection function. users can distinguish the device connected to the usb ports is a dedicated charger, portable device, general usb interface or charging device with usb interface by monitoring the voltage and current of the connected usb lines. d?- d??pl m u x pds5[1:0] pd5 m u x vdd dac3rv ?-?it dac3 dac3o? aduda3[7:0] d?+ d?ppl m u x pds4[1:0] pd4 usw? m u x vdd dac?rv ?-?it dac? dac?o? aduda?[7:0] d1- d1?pl m u x pd3 m u x vdd dac1rv ?-?it dac1 dac1o? aduda1[7:0] d1+ d1ppl m u x pds?[1:0] pd? m u x vdd vref dac0rv ?-?it dac0 dac0o? aduda0[7:0] d0- d0?pl m u x pds1[1:0] pd1 d0+ d0ppl m u x pd0 usw1 d0psw pds0[1:0] v dp_src (0.?v) vdpo? v bg (lvrlvd) pds3[1:0] usb auto detection block diagram
rev. 1.00 140 ?ove??e? 1?? ?01? rev. 1.00 141 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu d0+/d0- for auto detection the d0+ line can output a voltage, v dp_src , with a value of 0.6v, which is enabled by setting the vdpon bit of aduc1 register and switched on by setting the d0ps bit in the aduc1 register. but it needs to note that only when the d0+ pin is set as an analog or digital input pin by writing the pin-shared function register bit a correct data, and then set the d0ps bit high, can the switch be on. when this port is connected to a dedicated charger, the 0.6v voltage can be output on the d0+ line. the d0+ and d0- lines are pin-shared with normal i/o function and a/d function determined by the pds0[1:0] and pds1[1:0] bits respectively in the pdps0 register. both the d0+ and d0- lines are internally connected a pull low resistor to vss which are controlled by the d0npl and d0ppl bits in the aduc2 register. d1+/d1- and d2+/d2- for auto detection there four 8-bit d/a converters, dacn, which is enabled by the dacnon bits in the aduc0 register. the d/a converter output signal is controlled by the adudan register value and the reference voltage which is selected by the dacnrv bit in the aduc0 register. there is an analog switch connected between the d1+ and d1- lines, which is controlled by the usw1 bit. similarly, there is an analog switch connected between the d2+ and d2- lines, which is controlled by the usw2 bit. but it needs to note that only when one of the d1+ and d1- or d2+ and d2- pins is in the analog or digital input type by setting the pin-shared function register, and then set the usw1or usw2 bit high, can the switch be on. the d1+ /d1- and d2+ /d2- lines are individually connected a pull low resistor respectively to vss which are controlled by the d1npl/d1ppl and d2npl/ d2ppl bits in the aduc2 register. usb auto detection registers overall operation of the usb auto detection function is controlled using several registers. register name bit 7 6 5 4 3 2 1 0 aduc0 dac3rv dac? rv dac1rv dac0rv dac3o? dac?o? dac1o? dac0o? aduc1 usw? usw1 vdpo? d0ps aduc? d??pl d?ppl d1?pl d1ppl d0?pl d0ppl aduda0 d7 d? d5 d4 d3 d? d1 d0 aduda1 d7 d? d5 d4 d3 d? d1 d0 aduda? d7 d? d5 d4 d3 d? d1 d0 aduda3 d7 d? d5 d4 d3 d? d1 d0 usb auto detection register list
rev. 1.00 140 ?ove??e? 1?? ?01? rev. 1.00 141 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu aduc0 register bit 7 6 5 4 3 2 1 0 ?a?e dac3rv dac? rv dac1rv dac0rv dac3o? dac?o? dac1o? dac0o? r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 dac3rv : dac3 reference voltage selection 0: from vdd pin 1: from vref pin bit 6 dac2rv : dac2 reference voltage selection 0: from vdd pin 1: from vref pin bit 5 dac1rv : dac1 reference voltage selection 0: from vdd pin 1: from vref pin bit 4 dac0rv : dac0 reference voltage selection 0: from vdd pin 1: from vref pin bit 3 dac3on : dac3 enable control 0: disable 1: enable bit 2 dac2on : dac2 enable control 0: disable 1: enable bit 1 dac1on : dac1 enable control 0: disable 1: enable bit 0 dac0on : dac0 enable control 0: disable 1: enable
rev. 1.00 14? ?ove??e? 1?? ?01? rev. 1.00 143 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu aduc1 register bit 7 6 5 4 3 2 1 0 ?a?e usw? usw1 vdpo? d0ps r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 usw2 : usw2 switch control 0: switch off 1: switch on this bit controls the usw2 switch on/off. but only when one of the d2+ and d2- pins is used as the analog or digital input pin by setting the pin-shared function register, and then set the usw2 bit high, can the switch be on. bit 2 usw1 : usw1 switch control 0: switch off 1: switch on this bit controls the usw1 switch on/off. but only when one of the d1+ and d1- pins is used as the analog or digital input pin by setting the pin-shared function register, and then set the usw1 bit high, can the switch be on. bit 1 vdpon : v dp_src voltage enable control 0: disable 1: enable bit 0 d0ps : d0psw switch control 0: switch off 1: switch on this bit controls the d0psw switch on/off. but only when the d0+ pin is used as the analog or digital input pin by setting the pin-shared function register, and then set the d0ps bit high, can the switch be on. adu c2 register bit 7 6 5 4 3 2 1 0 ?a?e d??pl d?ppl d1?pl d1ppl d0?pl d0ppl r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0. bit 5 d2npl : d2- pin pull-low control 0: disable 1: enable bit 4 d2ppl : d2+ pin pull-low control 0: disable 1: enable bit 3 d1npl : d1- pin pull-low control 0: disable 1: enable bit 2 d1ppl : d1+ pin pull-low control 0: disable 1: enable bit 1 d0npl : d0- pin pull-low control 0: disable 1: enable bit 0 d0ppl : d0+ pin pull-low control 0: disable 1: enable
rev. 1.00 14? ?ove??e? 1?? ?01? rev. 1.00 143 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu aduda0 register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : 8-bit dac0 output control data bits dac0 output=(dac0 reference voltage) (aduda0 [7:0]) / 256 aduda 1 register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : 8-bit dac1 output control data bits dac1 output=(dac1 reference voltage) (aduda1 [7:0]) / 256 aduda 2 register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : 8-bit dac2 output control data bits dac2 output=(dac2 reference voltage) (aduda2 [7:0]) / 256 aduda 3 register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : 8-bit dac3 output control data bits dac3 output=(dac3 reference voltage) (aduda3 [7:0]) / 256
rev. 1.00 144 ?ove??e? 1?? ?01? rev. 1.00 145 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu serial interface module C sim the device contains a serial interface module, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash memory, etc. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o pins are selected using pull-high control registers when the sim function is enabled and the corresponding pins are used as sim input pins. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spi interface specifcation can control multiple slave devices from a single master, but this device is provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. sck spi master sdo sdi scs sck spi slave sdi sdo scs spi master/slave connection spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines ; sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin- shared with normal i/o pins and with the i 2 c function pins, the spi interface must frst be enabled by setting the correct bits in the simc0 and simc2 registers. the spi can be disabled or enabled using the simen bit in the simc0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock sign al. as the devic e only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to "1" to enable scs pin function, set csen bit to "0" the scs pin will be foating state. the spi function in the device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen.
rev. 1.00 144 ?ove??e? 1?? ?01? rev. 1.00 145 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu simd tx/rx shift register sdi pin clock edge/polarity control ckeg bit ckpolb bit clock source select f sys f sub stm ccrp match frequency/2 sck pin csen bit busy status sdo pin wcol flag trf flag scs pin data bus spi block diagram spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim? sim1 sim0 simdeb1 simdeb0 sime? simicf simd d7 d? d5 d4 d3 d? d1 d0 simc? d7 d? ckpolb ckeg mls cse? wcol trf sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. ? simd register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmission clock frequency. although not connected with the spi function, the simc0 register is also used to control the peripheral clock prescaler. register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc.
rev. 1.00 14? ?ove??e? 1?? ?01? rev. 1.00 147 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ? simc0 register bit 7 6 5 4 3 2 1 0 ?a?e sim? sim1 sim0 simdeb1 simdeb0 sime? simicf r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is stm ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from f sub or the stm. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as "0" bit 3~2 simdeb[1 :0]: i 2 c debounce time selection the simdeb[1:0] bits are of no used in spi mode of sim, please ignore these selection bits when operate in spi mode. bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 simicf : sim incomplete flag 0: sim incompleted is not occurred 1: sim incompleted is occurred the simicf bit is determined by scs pin. when scs pin is set high, it will clear the spi counter. meanwhile, the interrupt is occurred and the incomplete fag, simicf, is set high.
rev. 1.00 14? ?ove??e? 1?? ?01? rev. 1.00 147 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ? simc2 register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? ckpolb ckeg mls cse? wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 d7~d6 : undefned bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and placed into a foating condition. if the bit is high the scs pin will be enabled and used as a select pin. bit 1 wcol : spi write collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. bit 0 trf : spi transmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the transmit/receive complete fag and is set high automatically when an spi data transmission is completed, but must cleared to zero by the application program. it can be used to generate an interrupt.
rev. 1.00 14? ?ove??e? 1?? ?01? rev. 1.00 149 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function in special idle modes if the clock source used by the spi interface is still active. sck (ckpolb=1? ckeg=0) sck (ckpolb=0? ckeg=0) sck (ckpolb=1? ckeg=1) sck (ckpolb=0? ckeg=1) scs sdo (ckeg=0) sdo (ckeg=1) sdi data captu?e w?ite to simd sime?? cse?=1 sime?=1? cse?=0 (exte?nal pull-high) d7/d0 d?/d1 d5/d? d4/d3 d3/d4 d?/d5 d1/d? d0/d7 d7/d0 d?/d1 d5/d? d4/d3 d3/d4 d?/d5 d1/d? d0/d7 spi master mode timing sck (ckpolb=1) sck (ckpolb=0) scs sdo sdi data captu?e w?ite to simd (sdo does not change until fi?st sck edge) d7/d0 d?/d1 d5/d? d4/d3 d3/d4 d?/d5 d1/d? d0/d7 spi slave mode timing C ckeg=0
rev. 1.00 14? ?ove??e? 1?? ?01? rev. 1.00 149 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu sck (ckpolb=1) sck (ckpolb=0) scs sdo sdi data captu?e d7/d0 d?/d1 d5/d? d4/d3 d3/d4 d?/d5 d1/d? d0/d7 w?ite to simd (sdo changes as soon as w?iting o ccu?s; sdo is floating if scs=1) ?ote: fo? spi slave ?ode? if sime?= 1 and cse?=0? spi is always ena?led and igno?es the scs level. spi slave mode timing C ckeg=1 clea? wcol w?ite data into simd wcol=1? t?ans?ission co?pleted? (trf=1?) read data f?o? simd clea? trf e?d t?ansfe? finished? a spi t?ansfe? maste? o? slave ? sime?=1 configu?e ckpolb? ckeg? cse? and mls a sim[?:0]=000? 001? 010? 011 o? 100 sim[?:0]=101 maste? slave y y ? ? ? y spi transfer control flowchart
rev. 1.00 150 ?ove??e? 1?? ?01? rev. 1.00 151 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. device slave device maste? device slave vdd sda scl i 2 c master/slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data; however, it is the master device that has overall control of the bus. for the device, wh ich only operate in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. the pull-up control function pin-shared with scl/sda pin is still applicable even if i 2 c device is activated and the related internal pull-up register could be controlled by its corresponding pull-up control register.

? ? ? ? ?? - ? ? ? ? ?? ? ? ? - ? ? ? ? ? ? ? ? ? ? ? ?? - ? ? ? ? ??
? ?? ? i 2 c block diagram
rev. 1.00 150 ?ove??e? 1?? ?01? rev. 1.00 151 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu
i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and simtoc, one address register, sima and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. the simtoc register is used for i 2 c time-out control. register name bit 7 6 5 4 3 2 1 0 simc0 sim? sim1 sim0 simdeb1 simdeb0 sime? simicf simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d? d5 d4 d3 d? d1 d0 sima a? a5 a4 a3 a? a1 a0 d0 simtoc simtoe ? simtof simtos5 simtos4 simtos3 simtos ? simtos1 simtos0 i 2 c register list ? simc0 register bit 7 6 5 4 3 2 1 0 ?a?e sim? sim1 sim0 simdb?c1 simdb?c0 sime? simicf r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is stm ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from f sub or the stm. if the spi slave mode is selected then the clock will be supplied by an external master device.
rev. 1.00 15? ?ove??e? 1?? ?01? rev. 1.00 153 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 4 unimplemented, read as "0" bit 3~2 simdeb1~simdeb0 : i 2 c debounce time selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 simicf : sim incomplete flag simicf is of no used in i 2 c mode of sim, please ignore this fag when operate in i 2 c mode. ? simc1 register bit 7 6 5 4 3 2 1 0 ?a?e hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c bus address match fag 0: not address match 1: address match the haas fag is the address match fag. this fag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb fag is the i 2 c busy fag. this fag will be "1" when the i 2 c bus is busy which will occur when a start signal is detected. the fag will be cleared to zero when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter
rev. 1.00 15? ?ove??e? 1?? ?01? rev. 1.00 153 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to "0" before further data is received. bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is the i 2 c slave read/write flag. this flag determines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the srw fag to determine whether it should be in transmit mode or receive mode. if the srw fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i 2 c address match wake up function control 0: disable 1: enable . this bit should be set to 1 to enable the i 2 c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correct device operation. bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receives acknowledge fag 1: slave does not receive acknowledge fag the rxak flag is the receiver acknowledge flag. when the rxak flag is "0", it means that a acknowledge signal has been received at the 9 th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receive wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak fag is "1". when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device write data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the device can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. ? simd register bit 7 6 5 4 3 2 1 0 ?a?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown
rev. 1.00 154 ?ove??e? 1?? ?01? rev. 1.00 155 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu ? sima register bit 7 6 5 4 3 2 1 0 ?a?e a? a5 a4 a3 a? a1 a0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~1 a6~a0 : i 2 c slave address a6~ a0 is the i 2 c slave address bit 6 ~ bit 0. the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bit7~ bit1 of the sima register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit this bit can be read or written by user software program. simtoc register bit 7 6 5 4 3 2 1 0 ?a?e simtoe ? simtof simtos5 simtos4 simtos3 simtos ? simtos1 simtos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 simtoen : i 2 c interface time-out control 0: disable 1: enable bit 6 simtof : i 2 c interface time-out fag 0: no occurred 1: occurred the simtof fag is set by the time-out circuitry when the time-out event occurs and cleared by software program. bit 5~0 simtos5~simtos0 : i 2 c interface time-out period selection the i 2 c time-out clock source is f sub /32. the i 2 c time-out time is ([simtos5:simtos0] + 1) (32/f sub )
rev. 1.00 154 ?ove??e? 1?? ?01? rev. 1.00 155 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmission, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit and simtof bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer or from the i 2 c communication time-out. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/ write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 bits to "110" and the simen bits to "1" in the simc0 register to enable the i 2 c bus. ? step 2 write the slave address to the i 2 c bus address register sima. ? step 3 set the sime interrupt enable bit o enable the sim interrupt. set sim[2:0]=110 set simen write slave address to sima i 2 c bus interrupt=? clr sime poll simf to decide when to go to i 2 c bus isr no yes set sime wait for interrupt goto main program goto main program start i 2 c bus initialisation flow chart
rev. 1.00 15? ?ove??e? 1?? ?01? rev. 1.00 157 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defnes the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from three sources, when the program enters the interrupt subroutine, the haas bit and simtof bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer or from the i 2 c communication time-out. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the srw bit in the simc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw fag is "1" then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw fag is "0" then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the srw fag to determine if it is to be a transmitter or a receiver. if the srw fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set high. if the srw fag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be cleared to zero.
rev. 1.00 15? ?ove??e? 1?? ?01? rev. 1.00 157 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. sta?t scl sda scl sda 1 s=sta?t (1 ?it) sa=slave add?ess (7 ?its) sr=srw ?it (1 ?it) m=slave device send acknowledge ?it (1 ?it) d=data (? ?its) a=ack (rxak ?it fo? t?ans?itte?? txak ?it fo? ?eceive?? 1 ?it) p=stop (1 ?it) 0 ack slave add?ess srw stop data ack 1101010 10010100 s sa sr m d a d a s sa sr m d a d a p i 2 c communication timing diagram note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
rev. 1.00 15? ?ove??e? 1?? ?01? rev. 1.00 159 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu sta?t simtof=1? set simtoe? clr simtof reti haas=1? htx=1? srw=1? read f?o? simd to ?elease scl line reti rxak=1? w?ite data to simd to ?elease scl line clr htx clr txak du??y ?ead f?o? simd to ?elease scl line reti reti set htx w?ite data to simd to ?elease scl line reti clr htx clr txak du??y ?ead f?o? simd to ?elease scl line reti yes ?o ?o yes yes ?o yes ?o ?o yes i 2 c bus isr flow chart
rev. 1.00 15? ?ove??e? 1?? ?01? rev. 1.00 159 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu i 2 c time out function in order to reduce the i 2 c lockup problem due to reception of erroneous clock sources, a time-out function is provided. if the clock source connected to the i 2 c bus is not received for a while, then the i 2 c circuitry and the simc1 register will be reset, the simtof bit in the simtoc register will be set high after a certain time-out period. the time out function enable/disable and the time-out period are managed by the simtoc register. ? i 2 c time out operation the time-out counter starts to count on an i 2 c bus "start" & "address match" condition, and is cleared by an scl falling edge. before the next scl falling edge arrives, if the time elapsed is greater than the time-out period specifed by the simtoc register, then a time-out condition will occur. the time-out function will stop when an i 2 c "stop" condition occurs. there are 64 time-out period selections which can be selected using the simtos0~simtos5 bits in the simtoc register. sta?t scl sda scl sda 1 0 ack slave add?ess srw stop 1101010 10010100 i ? c ti?e-out counte? sta?t i ? c ti?e-out counte? ?eset on scl negative t?ansition i 2 c time-out diagram when an i 2 c time-out counter overfow occurs, the counter will stop and the simtoen bit will be cleared to zero and the simtof bit will be set high to indicate that a time-out condition has occurred. when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out simd? sima? simc0 ?o change simc1 reset to por condition i 2 c registers after time-out
rev. 1.00 1?0 ?ove??e? 1?? ?01? rev. 1.00 1?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lcd scom function the device has the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with certain pin on the i/o ports. the lcd signals(com and seg) are generated using the application program. lcd operation an external lcd panel can be driven using this device by configuring the i/o pins as common pins and segment pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1/2 bias operation. the scomen bit in the scomc register is the overall master control for the lcd driver. the lcd scomn pin is selected to be used for lcd driving by the corresponding pin-shared function selection bits. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation.
lcd com bias lcd bias current control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which are being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the scomc register. scomc register bit 7 6 5 4 3 2 1 0 ?a?e isel1 isel0 scome? r/w r/w r/w r/w por 0 0 0 bit 7 unimplemented, read as "0" bit 6~5 isel1~isel0 : select r type lcd bias current (v dd =5v) 00: 2100k (1/2 bias), i bias =25a 01: 250k (1/2 bias), i bias =50a 10: 225k (1/2 bias), i bias =100a 11: 212.5k (1/2 bias), i bias =200a bit 4 scomen : lcd function enable control bit 0: disable 1: enable when scomen is set, it will turn on the dc path of resistor to generate 1/2 v dd bias voltage. bit 3~0 unimplemented, read as "0"
rev. 1.00 1?0 ?ove??e? 1?? ?01? rev. 1.00 1?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupt functions. the external interrupts are generated by the action of the external int0~int2 pins, while the internal interrupts are generated by various internal functions such as the timer modules(tms) , time base s , serial interface module (sim), over current protections (ocp), over voltage protections (ovp), under voltage protections (uvp), l ow voltage detector (lvd), eeprom and the a/d converter. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory. the registers fall into three categories. the frst is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~ mfi1 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt s trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "e" for enable/disable bit or "f" for request fag. function enable bit request flag notes glo?al emi i?tn pin i?tne i?tnf n=0~? ove? cu??ent p?otection ocpne ocpnf n=0 o? 1 unde? voltage p?otection uvpne uvpnf n=0 o? 1 ove? voltage p?otection ovpne ovpnf n=0 o? 1 multi-function mfne mfnf n=0 o? 1 a/d conve?te? ade adf ti ?e base tbne tbnf n=0 o? 1 lvd lve lvf eeprom dee def sim sime simf stm stmpe stmpf stmae stmaf ptm ptmpe ptmpf ptmae ptmaf interrupt register bit naming conventions
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu register name bit 7 6 5 4 3 2 1 0 i?teg i?t?s1 i?t?s0 i?t1s1 i?t1s0 i?t0s1 i?t0s0 i?tc0 ovp0f ocp1f ocp0f ovp0e ocp1e ocp0e emi i?tc1 i?t0f uvp1f uvp0f ovp1f i?t0e uvp1e uvp0e ovp1e i?tc? mf1f mf0f i?t?f i?t1f mf1e mf0e i?t?e i?t1e i?tc3 simf tb1f tb0f lvf sime tb1e tb0e lve mfi0 def stmaf stmpf dee stmae stmpe mfi1 adf ptmaf ptmpf ade ptmae ptmpe interrupt register list integ register bit 7 6 5 4 3 2 1 0 ?a?e i?t?s1 i?t?s0 i?t1s1 i?t1s0 i?t0s1 i?t0s0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~4 int2s1~int2s0 : interrupt edge control for int2 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 3~2 int1s1~int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges intc0 register bit 7 6 5 4 3 2 1 0 ?a?e ovp0f ocp1f ocp0f ovp0e ocp1e ocp0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 ovp0f : over voltage protection 0 interrupt request fag 0: no request 1: interrupt request bit 5 ocp1f : over current protection 1 interrupt request fag 0: no request 1: interrupt request bit 4 ocp0f : over current protection 0 interrupt request fag 0: no request 1: interrupt request bit 3 ovp0e : over voltage protection 0 interrupt control 0: disable 1: enable
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 2 ocp1e : over current protection 1 interrupt control 0: disable 1: enable bit 1 ocp0e : over current protection 0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable intc1 register bit 7 6 5 4 3 2 1 0 ?a?e i?t0f uvp1f uvp0f ovp1f i?t0e uvp1e uvp0e ovp1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 6 uvp1f : under voltage protection 1 interrupt request fag 0: no request 1: interrupt request bit 5 uvp0f : under voltage protection 0 interrupt request fag 0: no request 1: interrupt request bit 4 ovp1f : over voltage protection 1 interrupt request fag 0: no request 1: interrupt request bit 3 int0e : int0 interrupt control 0: disable 1: enable bit 2 uvp1e : under voltage protection 1 interrupt control 0: disable 1: enable bit 1 uvp0e : under voltage protection 0 interrupt control 0: disable 1: enable bit 0 ovp1e : over voltage protection 1 interrupt control 0: disable 1: enable intc2 register bit 7 6 5 4 3 2 1 0 ?a?e mf1f mf0f i?t?f i?t1f mf1e mf0e i?t?e i?t1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf1f : multi-function interrupt 1 request fag 0: no request 1: interrupt request bit 6 mf0f : multi-function interrupt 0 request fag 0: no request 1: interrupt request
rev. 1.00 1?4 ?ove??e? 1?? ?01? rev. 1.00 1?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu bit 5 int2f : int2 interrupt request fag 0: no request 1: interrupt request bit 4 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 3 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 2 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 1 int2e : int2 interrupt control 0: disable 1: enable bit 0 int1e : int1 interrupt control 0: disable 1: enable intc 3 register bit 7 6 5 4 3 2 1 0 ?a?e simf tb1f tb0f lvf sime tb1e tb0e lve r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 simf : serial interface module interrupt request fag 0: no request 1: interrupt request bit 6 tb1f : time base 1 interrupt request fag 0: no request 1: interrupt request bit 5 tb0f : time base 0 interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3 sime : serial interface module interrupt control 0: disable 1: enable bit 2 tb1e : time base 1 interrupt control 0: disable 1: enable bit 1 tb0e : time base 0 interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable
rev. 1.00 1?4 ?ove??e? 1?? ?01? rev. 1.00 1?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu mfi0 register bit 7 6 5 4 3 2 1 0 ?a?e def stmaf stmpf dee stmae stmpe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 5 stmaf : stm comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 stmpf : stm comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as "0" bit 2 dee : data eeprom interrupt control 0: disable 1: enable bit 1 stmae : stm comparator a match interrupt control 0: disable 1: enable bit 0 stmpe : stm comparator p match interrupt control 0: disable 1: enable mfi 1 register bit 7 6 5 4 3 2 1 0 ?a?e adf ptmaf ptmpf ade ptmae ptmpe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 adf : a/d converter interrupt request fag 0: no request 1: interrupt request bit 5 ptmaf : ptm comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ptmpf : ptm comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as "0" bit 2 ade : a/d converter interrupt control 0: disable 1: enable bit 1 ptmae : ptm comparator a match interrupt control 0: disable 1: enable bit 0 ptmpe : ptm comparator p match interrupt control 0: disable 1: enable
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p, comparator a match or a/d conversion completion etc., the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a "jmp" which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti", which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request fags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu inte??upt ?a?e request flags ena?le bits maste? ena?le vecto? emi auto disa?led in isr p?io?ity high low inte??upts contained within multi-function inte??upts xxe ena?le bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr m. funct. 0 mf0f mf0e emi emi m. funct. 1 mf1f mf1e ??h ?ch stm p stmpf stmpe stm a stmaf stmae ptm p ptmpf ptmpe ptm a ptmaf ptmae 04h ocp0 ocp0f ocp0e emi ?0h i?t1 pin i?t1f i?t1e emi emi 0?h ocp1 ocp1f ocp1e ti?e base 0 tb0f tb0e emi 34h ti?e base 1 tb1f tb1e emi 3?h 3ch sim simf sime emi inte??upt ?a?e request flags ena?le bits emi och ovp0 ovp0f ovp0e emi 10h ovp1 ovp1f ovp1e emi 14h uvp0 uvp0f uvp0e emi 1?h uvp1 uvp1f uvp1e 1ch i?t0 pin i?t0f i?t0e emi ?4h i?t? pin i?t?f i?t?e emi eeprom def dee a/d cove?te? adf ade emi lvd lvf lve 30h interrupt structure
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu external interrupts the external interrupts are controlled by signal transitions on the pins int0~int 2 . an external interrupt request will take place when the external interrupt request fags, int0f~int 2 f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int 2 e, must first be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be confgured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. t he pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request flags, int0f~int 2 f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull- high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. over current protection interrupts the ocp n interrupt is controlled by detecting the ocpn input current. an ocp n interrupt request will take place when the ocp n interrupt request flag, ocp n f, is set, which occurs when a large current is detected. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and ocp n interrupt enable bit, ocp n e, must frst be set. when the interrupt is enabled, the stack is not full and a n over current is detected, a subroutine call to the ocp n interrupt vector, will take place. when the interrupt is serviced, the ocp n interrupt fag, ocp n f, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. over voltage protection interrupts the o v p n interrupt is controlled by detecting the ovpn input voltage . an o v p n interrupt request will take place when the o v p n interrupt request fag, o v p n f, is set, which occurs when the over voltage protection circuit detects an over voltage condition . to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and o v p n interrupt enable bit, o v p n e, must frst be set. when the interrupt is enabled, the stack is not full and a n over voltage is detected, a subroutine call to the o v p n interrupt vector, will take place. when the interrupt is serviced, the o v p n interrupt fag, o v p n f, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu under voltage protection interrupts the uv p n interrupt is controlled by detecting the uvpn input voltage . an uv p n interrupt request will take place when the uv p n interrupt request fag, uv p n f, is set, which occurs when the under voltage protection circuit detects an under voltage condition . to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and uv p n interrupt enable bit, uv p n e, must first be set. when the interrupt is enabled, the stack is not full and a n under voltage is detected, a subroutine call to the uv p n interrupt vector, will take place. when the interrupt is serviced, the uv p n interrupt fag, uv p n f, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. multi-function interrupts within this device there are two multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts , eeprom interrupt and a/d converter interrupt . a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt fags will be automatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts will not be automatically reset and must be manually reset by the application program. timer module interrupts each of t he standard type tm and periodic type tm ha s two interrupts. all of the tm interrupts are contained within the multi-function interrupts. for the standard type tm and the periodic type tm , each has two interrupt request fags of stmpf, stmaf and ptmpf, ptmaf and two enable bits of stmpe, stmae and ptmpe, ptmae . a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program.
rev. 1.00 170 ?ove??e? 1?? ?01? rev. 1.00 171 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu eeprom interrupt the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def, is set, which occurs when an eeprom write cycle ends. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom write cycle ends, a subroutine call to the respective eeprom interrupt vector will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. a/d converter interrupt the a/d converter interrupt is also contained within the multi-function interrupt. the a/d converter interrupt is c ontrolled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the a/d converter interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the a/d converter interrupt fag bit, adf will not be automatically cleared , it has to be cleared by the application program. time base interrupts the function of the time base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section.

rev. 1.00 170 ?ove??e? 1?? ?01? rev. 1.00 171 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu tbc register bit 7 6 5 4 3 2 1 0 ?a?e tbo? tbck tb11 tb10 tb0? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 bit 7 tbon : time base 0 and time base 1 control bit 0: disable 1: enable bit 6 tbck : f tb clock source selection 0: f tbc 1: f sys /4 bit 5~4 tb11 ~ tb10 : select time base 1 time-out period 00: 2 12 /f tb 01: 2 13 / f tb 10: 2 14 /f tb 11: 2 15 / f tb bit 3 unimplemented, read as "0" bit 2~0 tb02~tb00 : select time base 0 time-out period 000: 2 8 /f tb 001: 2 9 /f tb 010: 2 10 /f tb 011: 2 11 /f tb 100: 2 12 /f tb 101: 2 13 /f tb 110: 2 14 /f tb 111: 2 15 /f tb lvd interrupt an lvd interrupt request will take place when the lvd interrupt request fag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and low voltage interrupt enable bit, lve, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the lvd interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the lvd interrupt request fag, lvf, will be also automatically cleared. serial interface module interrupt the serial interface module interrupt is also known as the sim interrupt. a sim interrupt request will take place when the sim interrupt request flag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface, an i 2 c address match or i 2 c time-out occurrence. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, must first be set. when the interrupt is enabled, the stack is not full and any of the above described situations occurs, a subroutine call to the sim interrupt vector, will take place. when the sim interface interrupt is serviced, the interrupt request fag, simf, will be automatically reset and the emi bit will be cleared to disable other interrupts.
rev. 1.00 17? ?ove??e? 1?? ?01? rev. 1.00 173 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltage may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the "call" instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 17? ?ove??e? 1?? ?01? rev. 1.00 173 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu low voltage detector C lvd t he device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be determined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 ?a?e lvdo lvde ? vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 lvdo : lvd output flag 0: no low voltage detect ed 1: low voltage detect ed bit 4 lvden : low voltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 vlvd2~vlvd0 : select lvd voltage 000: undefned 001: undefned 010: undefned 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.00 174 ?ove??e? 1?? ?01? rev. 1.00 175 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.7v and 4.0v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. vdd lvde? lvdo v lvd t lvds lvd operation the low voltage detector also has its own interrupt , providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. in this case, the lvf interrupt request flag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. when lvd function is enabled, it is recommenced to clear lvd fag frst, and then enables interrupt function to avoid mistake action.
rev. 1.00 174 ?ove??e? 1?? ?01? rev. 1.00 175 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu application circuits c12 0.1uf rs2 20mr r26 510r c16 0.1uf d- d+ id gnd vb us usb in micro usb q 20 rcr1523 r31 4.7k 1% q 19 2n 7002k r32 5.1k 1% r33 100k r34 10k c22 0.1uf r30 30k +3v r27 2k r28 10k q 18 ss m3j 328r r29 30k q 17 ss m3j 328r r4 20r c4 1nf c2 0.1uf c1 47uf/ 10v s s d d d d s g q6 ao 4435 pmos r6 30k s s d d d d s g q7 ao 4468 n mos r7 30k l1 3.3uh/ 6a c3 47uf/ 10v bat1 r1 330r bat+ r2 1k c7 0.1uf vb us d- d+ gnd usb o ut t yp e a vin r24 2k r23 10k q 13 ss m3j 328r r25 30k q 14 ss m3j 328r c17 0.1uf r16 510r rs3 20mr c20 0.1uf r17 30k l2 3.3uh/ 6a c9 47uf/ 10v r9 30k r8 30k r5 20r c11 1nf c8 0.1uf c10 47uf/ 10v r3 20r c5 0.1uf r18 1k c15 1nf c14 0.1uf c13 4.7uf d3 ss 14 m cu_ vdd bat+ r14 1m c18 1uf c19 1uf r13 1m q 10 8050 sw1 r12 4.7k hv_out1 hv_out1 hv_out2 r20 47r d2 ss 14 d4 ss 14 vin d1 bat 54c +3v w _led1 r19 51r m cu_ vdd r10 680r led3 led4 r11 680r led1 led2 r15 10k g1 g2 d2 s1 d1 s2 q11 fs8205 s1 g1 d1 d1 d2 d2 s2 g2 q8 mt4953 pmos g1 s1 s1 d s2 s2 d g2 q9 8205a n mos td v cc gnd oc cs od u2 dw 01 s2 g2 s2 s1 s2 g1 d d q1 8205a s2 g2 s2 s1 s2 g1 d d q2 8205a s2 g2 s2 s1 s2 g1 d d q3 8205a s2 g2 s2 s1 s2 g1 d d q4 8205a s2 g2 s2 s1 s2 g1 d d q5 8205a oc od oc oc oc oc oc od od od od od pd6 pd7 pd0/an 0/ d0+ pd1/an 1/ d0- pd2/an 2/ d1+ pd3/an 3/ d1- pd4/an 4/ d2+ pd5/an 5/ d2- pa7 pa 6/int1 pa1/o uv p0/an 10 pa0/o uv p1/an 11 pa 3/batv/an8 pa 2/an9/v ref pc1/o cp00 pc2/o cp10 pc3/o cp11 pc4 lead pa4 pa5 v dd vss pb0/o ut 0h pb1/o ut 0l pb2/o ut 1h pb3/o ut 1l pb5/s com2 pb6/s com3 pb7/s com3 u1 HT45F5N gnd gnd gnd gnd rx 1+ rx1- vb us vbus vbus vbus sb u2 sbu1 d+ d+ d- d- cc2 cc1 tx 2+ tx 2- tx1- tx 1+ rx 2+ rx2- usb _c type
rev. 1.00 17? ?ove??e? 1?? ?01? rev. 1.00 177 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 17? ?ove??e? 1?? ?01? rev. 1.00 177 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction "ret" in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "halt" instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 17? ?ove??e? 1?? ?01? rev. 1.00 179 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu instruction set summary the instructions related to the data memory access in the following table can be used when the desired data memory is located in data memory sector 0. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a?[?] add data me?o? y to acc 1 z? c? ac? ov ? sc addm a?[?] add acc to data me ?o?y 1 ?ote z? c? ac? ov ? sc add a?x add i?? ediate data to acc 1 z? c? ac? ov ? sc adc a?[?] add data me?o? y to acc with ca??y 1 z? c? ac? ov ? sc adcm a?[?] add acc to data ?e?o?y with ca??y 1 ?ote z? c? ac? ov ? sc sub a?x su?t?act i??ediate data f?o? the acc 1 z? c? ac? ov ? sc? cz sub a?[?] su?t?act data me?o?y f?o? acc 1 z? c? ac? ov ? sc? cz subm a?[?] su?t?act data me?o?y f?o? acc with ?esult in data me?o?y 1 ?ote z? c? ac? ov ? sc? cz sbc a?x su?t?act i??ediate data f?o? acc with ca??y 1 z? c? ac? ov ? sc? cz sbc a?[?] su?t?act data me?o?y f?o? acc with ca??y 1 z? c? ac? ov ? sc? cz sbcm a?[?] su?t?act data me?o?y f?o? acc with ca??y ? ?esult in data me?o?y 1 ?ote z? c? ac? ov ? sc? cz daa [ ?] deci? al adjust acc fo? addition with ?esult in data me?o?y 1 ?ote c logic operation a?d a?[?] logical a ?d data me?o? y to acc 1 z or a?[?] logical or data me?o? y to acc 1 z xor a?[?] logical xor data me?o? y to acc 1 z a?dm a?[?] logical a ? d acc to data me?o?y 1 ?ote z orm a?[?] logical or acc to data me ?o?y 1 ?ote z xorm a?[?] logical xor acc to data me ?o?y 1 ?ote z a?d a?x logical a ?d i?? ediate data to acc 1 z or a?x logical or i?? ediate data to acc 1 z xor a?x logical xor i?? ediate data to acc 1 z cpl [ ?] co?ple?ent data me?o?y 1 ?ote z cpla [ ?] co?ple?ent data me?o?y with ? esult in acc 1 z increment & decrement i? ca [?] inc?e?ent data me?o?y with ? esult in acc 1 z i?c [?] inc?e?ent data me?o?y 1 ?ote z deca [ ?] dec?e?ent data me?o?y with ? esult in acc 1 z dec [?] dec?e?ent data me?o?y 1 ?ote z rotate rra [ ?] rotate data me?o?y ?ight with ? esult in acc 1 ?one rr [?] rotate data me?o?y ?ight 1 ?ote ?one rrca [ ?] rotate data me?o?y ?ight th?ough ca??y with ? esult in acc 1 c rrc [?] rotate data me?o?y ?ight th?ough ca??y 1 ?ote c rla [ ?] rotate data me?o?y left with ? esult in acc 1 ?one rl [ ?] rotate data me?o?y left 1 ?ote ?one rlca [ ?] rotate data me?o?y left th?ough ca??y with ? esult in acc 1 c rlc [?] rotate data me?o?y left th?ough ca??y 1 ?ote c
rev. 1.00 17? ?ove??e? 1?? ?01? rev. 1.00 179 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu mnemonic description cycles flag affected data move mov a ?[?] move data me?o? y to acc 1 ?one mov [?]?a move acc to data me ?o?y 1 ?ote ?one mov a ?x move i?? ediate data to acc 1 ?one bit operation clr [?].i clea? ?it of data me?o?y 1 ?ote ?one set [ ?].i set ?it of data me?o?y 1 ?ote ?one branch operation jmp add ? ju?p unconditionally ? ?one sz [?] skip if data me?o?y is ze?o 1 ?ote ?one sza [ ?] skip if data me?o?y is ze?o with data ?ove? ent to acc 1 ?ote ?one sz [?].i skip if ?it i of data me?o?y is ze?o 1 ?ote ?one s?z [?] skip if data me?o?y is not ze?o 1 ?ote ?one s?z [?].i skip if ?it i of data me?o?y is not ze?o 1 ?ote ?one siz [?] skip if inc?e?ent data me?o?y is ze?o 1 ?ote ?one sdz [?] skip if dec?e?ent data me?o?y is ze?o 1 ?ote ?one siza [ ?] skip if inc?e?ent data me?o?y is ze?o with ? esult in acc 1 ?ote ?one sdza [ ?] skip if dec?e?ent data me?o?y is ze?o with ? esult in acc 1 ?ote ?one call add ? su??outine call ? ?one ret retu?n f?o? su??outine ? ?one ret a ?x retu?n f?o? su??outine and load i?? ediate data to acc ? ?one reti retu?n f?o? inte??upt ? ?one table read operation tabrd [ ?] read table (specifc page) to tblh and data memory ? ?ote ?one tabrdl [ ?] read ta? le (last page) to tblh and data me?o?y ? ?ote ?one itabrd [ ?] increment table pointer tblp frst and read table to tblh and data memory ? ?ote ?one itabrdl [ ?] increment table pointer tblp frst and read table (last page) to tblh and data me?o?y ? ?ote ?one miscellaneous ?op ?o ope?ation 1 ?one clr [?] clea? data me?o?y 1 ?ote ?one set [ ?] set data me?o?y 1 ?ote ?one clr wdt clea? watchdog ti?e? 1 to ? pdf swap [ ?] swap ni??les of data me?o?y 1 ?ote ?one swapa [ ?] swap ni??les of data me?o?y with ? esult in acc 1 ?one halt ente? powe? down ?ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt" instruction the to and pdf fags may be affected by the execution status. the to and pdf fags are cleared after the "clr wdt" instructions is executed. otherwise the to and pdf fags remain unchanged.
rev. 1.00 1?0 ?ove??e? 1?? ?01? rev. 1.00 1?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu extended instruction set the extended instructions are used to support the full range address access for the data memory. when the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the cpu frmware performance. mnemonic description cycles flag affected arithmetic ladd a?[?] add data me?o? y to acc ? z? c? ac? ov ? sc laddm a?[?] add acc to data me ?o?y ? ?ote z? c? ac? ov ? sc ladc a?[?] add data me?o? y to acc with ca??y ? z? c? ac? ov ? sc ladcm a?[?] add acc to data ?e?o?y with ca??y ? ?ote z? c? ac? ov ? sc lsub a?[?] su?t?act data me?o?y f?o? acc ? z? c? ac? ov ? sc? cz lsubm a?[?] su?t?act data me?o?y f?o? acc with ?esult in data me?o?y ? ?ote z? c? ac? ov ? sc? cz lsbc a?[?] su?t?act data me?o?y f?o? acc with ca??y ? z? c? ac? ov ? sc? cz lsbcm a?[?] su?t?act data me?o?y f?o? acc with ca??y ? ?esult in data me?o?y ? ?ote z? c? ac? ov ? sc? cz ldaa [ ?] deci? al adjust acc fo? addition with ?esult in data me?o?y ? ?ote c logic operation la?d a?[?] logical a ?d data me?o? y to acc ? z lor a?[?] logical or data me?o? y to acc ? z lxor a?[?] logical xor data me?o? y to acc ? z la?dm a?[?] logical a ? d acc to data me?o?y ? ?ote z lorm a?[?] logical or acc to data me ?o?y ? ?ote z lxorm a?[?] logical xor acc to data me ?o?y ? ?ote z lcpl [ ?] co?ple?ent data me?o?y ? ?ote z lcpla [ ?] co?ple?ent data me?o?y with ? esult in acc ? z increment & decrement li? ca [?] inc?e?ent data me?o?y with ? esult in acc ? z li?c [?] inc?e?ent data me?o?y ? ?ote z ldeca [ ?] dec?e?ent data me?o?y with ? esult in acc ? z ldec [?] dec?e?ent data me?o?y ? ?ote z rotate lrra [ ?] rotate data me?o?y ?ight with ? esult in acc ? ?one lrr [?] rotate data me?o?y ?ight ? ?ote ?one lrrca [ ?] rotate data me?o?y ?ight th?ough ca??y with ? esult in acc ? c lrrc [?] rotate data me?o?y ?ight th?ough ca??y ? ?ote c lrla [ ?] rotate data me?o?y left with ? esult in acc ? ?one lrl [ ?] rotate data me?o?y left ? ?ote ?one lrlca [ ?] rotate data me?o?y left th?ough ca??y with ? esult in acc ? c lrlc [?] rotate data me?o?y left th?ough ca??y ? ?ote c data move lmov a?[?] move data me?o? y to acc ? ?one lmov [?]?a move acc to data me ?o?y ? ?ote ?one bit operation lclr [?].i clea? ?it of data me?o?y ? ?ote ?one lset [ ?].i set ?it of data me?o?y ? ?ote ?one
rev. 1.00 1?0 ?ove??e? 1?? ?01? rev. 1.00 1?1 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu mnemonic description cycles flag affected branch lsz [?] skip if data me?o?y is ze?o ? ?ote ?one lsza [ ?] skip if data me?o?y is ze?o with data ?ove? ent to acc ? ?ote ?one ls?z [?] skip if data me?o?y is not ze?o ? ?ote ?one lsz [?].i skip if ?it i of data me?o?y is ze?o ? ?ote ?one ls?z [?].i skip if ?it i of data me?o?y is not ze?o ? ?ote ?one lsiz [?] skip if inc?e?ent data me?o?y is ze?o ? ?ote ?one lsdz [?] skip if dec?e?ent data me?o?y is ze?o ? ?ote ?one lsiza [ ?] skip if inc?e?ent data me?o?y is ze?o with ? esult in acc ? ?ote ?one lsdza [ ?] skip if dec?e?ent data me?o?y is ze?o with ? esult in acc ? ?ote ?one table read ltabrd [ ?] read ta? le to tblh and data me?o?y 3 ?ote ?one ltabrdl [ ?] read ta? le (last page) to tblh and data me?o?y 3 ?ote ?one litabrd [ ?] increment table pointer tblp frst and read table to tblh and data memory 3 ?ote ?one litabrdl [ ?] increment table pointer tblp frst and read table (last page) to tblh and data me?o?y 3 ?ote ?one miscellaneous lclr [?] clea? data me?o?y ? ?ote ?one lset [ ?] set data me?o?y ? ?ote ?one lswap [ ?] swap ni??les of data me?o?y ? ?ote ?one lswapa [ ?] swap ni??les of data me?o?y with ? esult in acc ? ?one note: 1. for these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. any extended instruction which changes the contents of the pcl register will also require three cycles for execution.
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu instruction defnition adc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c, sc adcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c, sc add a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c, sc add a,x add immediate data to acc description the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. operation acc acc + x affected fag(s) ov, z, ac, c, sc addm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c, sc and a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specifed immediate data perform a bit wise logical and operation. the result is stored in the accumulator. operation acc acc and x affected fag(s) z andm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?3 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu call addr subroutine call description unconditionally calls a subroutine at the specifed address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specifed address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruction. operation stack program counter + 1 program counter addr affected fag(s) none clr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none clr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none clr wdt clear watchdog timer description the to, pdf fags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf cpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z cpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c
rev. 1.00 1?4 ?ove??e? 1?? ?01? rev. 1.00 1?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu dec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down fag pdf is set and the wdt time-out fag to is cleared. operation to 0 pdf 1 affected fag(s) to, pdf inc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specifed address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected fag(s) none mov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none mov a,x move immediate data to acc description the immediate data specifed is loaded into the accumulator. operation acc x affected fag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none
rev. 1.00 1?4 ?ove??e? 1?? ?01? rev. 1.00 1?5 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected fag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z or a,x logical or immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected fag(s) z orm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the restored address. operation program counter stack affected fag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specifed immediate data. program execution continues at the restored address. operation program counter stack acc x affected fag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by setting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected fag(s) none rl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu rla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none rlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c rr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none rra [m] rotate data memory right with result in acc description data in the specifed data memory is rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none rrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?7 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu rrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c sbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz sbc a, x subtract immediate data from acc with carry description the immediate data and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc - [m] - c affected fag(s) ov, z, ac, c, sc, cz sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz sdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu set [m] set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none set [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none snz [m].i skip if data memory is not 0 description if the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none snz [m] skip if data memory is not 0 description if the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m] 0 affected fag(s) none sub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c, sc, cz
rev. 1.00 1?? ?ove??e? 1?? ?01? rev. 1.00 1?9 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu subm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c, sc, cz sub a,x subtract immediate data from acc description the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? x affected fag(s) ov, z, ac, c, sc, cz swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none sz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none
rev. 1.00 190 ?ove??e? 1?? ?01? rev. 1.00 191 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu tabrd [m] read table (specifc page) to tblh and data memory description the low byte of the program code (specifc page) addressed by the table pointer pair (tblp and tbhp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none itabrd [m] increment table pointer low byte frst and read table to tblh and data memory description increment table pointer low byte, tblp, frst and then the program code addressed by the table pointer (tbhp and tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none itabrdl [m] increment table pointer low byte frst and read table (last page) to tblh and data memory description increment table pointer low byte, tblp, frst and then the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z xorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected fag(s) z
rev. 1.00 190 ?ove??e? 1?? ?01? rev. 1.00 191 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu extended instruction defnition the extended instructions are used to directly access the data stored in any data memory sections. ladc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c, sc ladcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c, sc ladd a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c, sc laddm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c, sc land a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z landm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z lclr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none lclr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none
rev. 1.00 19? ?ove??e? 1?? ?01? rev. 1.00 193 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lcpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z lcpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z ldaa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c ldec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z ldeca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z linc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z linca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z
rev. 1.00 19? ?ove??e? 1?? ?01? rev. 1.00 193 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lmov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none lmov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none lor a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z lorm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z lrl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none lrla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none lrlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c lrlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c
rev. 1.00 194 ?ove??e? 1?? ?01? rev. 1.00 195 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lrr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none lrra [m] rotate data memory right with result in acc description data in the specifed data memory is rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none lrrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c lrrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c lsbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz lsbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz
rev. 1.00 194 ?ove??e? 1?? ?01? rev. 1.00 195 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lsdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none lsdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none lset [m] set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none lset [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none lsiz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none lsiza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none lsnz [m].i skip if data memory is not 0 description if the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none
rev. 1.00 19? ?ove??e? 1?? ?01? rev. 1.00 197 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lsnz [m] skip if data memory is not 0 description if the content of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m] 0 affected fag(s) none lsub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c, sc, cz lsubm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c, sc, cz lswap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none lswapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none lsz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none lsza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none
rev. 1.00 19? ?ove??e? 1?? ?01? rev. 1.00 197 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu lsz [m].i skip i f bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none ltabrd [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none ltabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none litabrd [m] increment table pointer low byte frst and read table to tblh and data memory description increment table pointer low byte, tblp, frst and then the program code addressed by the table pointer (tbhp and tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none litabrdl [m] increment table pointer low byte frst and read table (last page) to tblh and data memory description increment table pointer low byte, tblp, frst and then the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none lxor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z lxorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z
rev. 1.00 19? ?ove??e? 1?? ?01? rev. 1.00 199 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information
rev. 1.00 19? ?ove??e? 1?? ?01? rev. 1.00 199 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.?3? bsc b 0.154 bsc c 0.00? 0.01? c 0.390 bsc d 0.0?9 e 0.0?5 bsc f 0.004 0.010 g 0.01? 0.050 h 0.004 0.010 0 ? symbol dimensions in mm min. nom. max. a ?.0 bsc b 3.9 bsc c 0.?0 0.30 c 9.9 bsc d 1.75 e 0.?35 bsc f 0.10 0.?5 g 0.41 1.?7 h 0.10 0.?5 0 ?
rev. 1.00 ?00 ?ove??e? 1?? ?01? rev. 1.00 ?01 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu saw type 32-pin (5mm5mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.0?? 0.030 0.031 a1 0.000 0.001 0.00? a3 0.00? bsc ? 0.007 0.010 0.01? d 0.193 0.197 0.?01 e 0.193 0.197 0.?01 e 0.0?0 bsc d? 0.1?? 0.1?? 0.130 e? 0.1?? 0.1?? 0.130 l 0.014 0.01? 0.01? k 0.00? symbol dimensions in mm min. nom. max. a 0.700 0.750 0.?00 a1 0.000 0.0?0 0.050 a3 0.?03 bsc ? 0.1?0 0.?50 0.300 d 4.900 5.000 5.100 e 4.900 5.000 5.100 e 0.50 bsc d? 3.10 3.?0 3.30 e? 3.10 3.?0 3.30 l 0.35 0.40 0.45 k 0.?0
rev. 1.00 ?00 ?ove??e? 1?? ?01? rev. 1.00 ?01 ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu saw type 46-pin (6.5mm4.5mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.031 0.033 0.035 a1 0.000 0.001 0.00? a3 0.00? bsc ? 0.00? 0.00? 0.010 d 0.?54 0.?5? 0.?5? e 0.175 0.177 0.179 e 0.01? bsc d? 0.197 0.?01 0.?05 e? 0.11 ? 0.1?? 0.1?? l 0.01? 0.01? 0.0?0 symbol dimensions in mm min. nom. max. a 0.?00 0.?50 0.900 a1 0.000 0.0?0 0.040 a3 0.?00 bsc ? 0.150 0.?00 0.?50 d ?.450 ?.500 ?.550 e 4.450 4.500 4.550 e 0.40 bsc d? 5.00 5.10 5.?0 e? 3.00 3.10 3.?0 l 0.30 0.40 0.50
rev. 1.00 ?0? ?ove??e? 1?? ?01? rev. 1.00 pb ?ove??e? 1?? ?01? HT45F5N/ht45fh5n power bank assp flash mcu HT45F5N/ht45fh5n power bank assp flash mcu copy?ight ? ?01? ? y holtek semico? ductor i?c. the info?? ation appea?ing in this data sheet is ?elieved to ?e accu? ate at the ti? e of pu ? lication. howeve ?? holtek assu? es no ?esponsi? ility a? ising f?o? the use of the specifcations described. the applications mentioned herein are used solely fo? the pu?pose of illust?ation and holtek ?akes no wa??anty o? ?ep?esentation that such applications will ? e suita? le without fu?the? ?odification? no? ?eco?? ends the use of its p?oducts fo? application that ?ay p?esent a ?isk to hu?an life due to ? alfunction o? othe? wise. holtek's p? oducts a? e not autho?ized fo? use as c? itical co?ponents in life suppo?t devices o? syste?s. holtek ?ese?ves the ?ight to alte? its products without prior notifcation. for the most up-to-date information, please visit ou? we? site at http://www.holtek.co? .tw.

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